Other Parts Discussed in Thread: TPS1663
Tool/software:
HI,DEAR.
AS BELOW, IT IS MY SCHEMATICS DESIGN.
THE SITUATION IS THAT VDD_OUT IS ABOUT 24V INPUT. VDD_CAP IS CONNECTED TO ALUMINUM ELECTROLYTIC CAPACITOR ARRAY (TOTAL VOLUME IS 23000UF).
ONCE VDD_OUT IS PRESENT, THE CAPACITORS CAN BE CHARGED TO 24V. IT IS RIGHT.
BUT AFTER A WHILE, THE VOLTAGE OF CAPACITORS IS FALLING SLOWLY TO 2V OR BELOW,EVEN IF THE INPUT OF VDD_OUT IS PRESENT.
IS IT NORMAL? I THINK THAT THE VOLTAGE OF CAPACITORS SHOULD BE STABLE AS LONG AS VDD_OUT IS PRESENT.
THANK YOU!