Tool/software:
Hi Team,
Currently, customer is working on the EMC test. Unfortunately, the test results are not good enough to meet the requirements. Therefore, they are trying to solve this issue.
Customer have measured some waveforms, and they are NOT “clean.” Could you have a look?
We can see that:
- Regarding the Vgs signal, there are overshoots and undershoots. I think it is affected by noise because the waveform measured when the load is off is clean and correct.
- Regarding the VDS signal, there are positive and negative spikes as well.
- Both Vgs and VDS are continuous with a stable frequency of 264kHz, so they can be triggered.
- There is a peak at around 47MHz which is over 52dBμV. According to the test, we know that it is from the boost converter.
To solve the EMC issue, I would like to modify the circuit design and do some testing before redesigning the PCB layout.
- Please refer to the schematic attached to this email. It is the current design.
- Please note that the inductor has been changed to 10μH from 6.8μH. The switching frequency has been reduced to 264kHz from 350kHz.
- Increase Rg. I have increased Rg from 5R1 to 10R0. It helps to reduce the peak by 5dBμV. I am considering increasing it to 33R or up to 100R. It looks like the rising edge of the Vgs is still very sharp.
- Reduce Rgs. I have added a resistor between the gate and source of each MOSFET. The value is 21k. I was hoping to eliminate the negative spike of VDS and the undershoot of the Vgs, but it hasn’t worked so far. I am considering reducing the Rgs to 10k.
- Add a 100pF (or pF level) ceramic capacitor as close as possible to each MOSFET.
- Adjust the resistance and capacitance of the snubber circuit. The capacitance will be reduced from 470nF to 470pF up to 22nF.
May I have your suggestion? Is there anything I can change to reduce the EMC peak?
Best Regards,
Ernest
