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UCC28951-Q1: Light load operation (<10% load current ) - Vout oscillation

BABU SANKARAN
Prodigy 55 points
Part Number: UCC28951-Q1
Other Parts Discussed in Thread: UCC28951

Tool/software:

Hello Team,

Spec: Vin - 80 to 120V  , Vout - 13.8V , Irated - 35A , Transformer TR - 4.5:1:1 , Fsw - 150kHz,  0.36V @ DCM , 

Following observation taken with 50% of scaled operational range.

  • We are observing Vout oscillation , when are operating with light load current of 2A to 4A (actual rating 35A).
  • We could observe COMP pin voltage droping below 0.8V & coming back after few cycle, so it shows burst mode operation.
  • As we are approaching maximum input voltage & same light load condition, Observing too much oscillation at Vout, COMP , SS & CS. Still Vout regulation happens as expected.
  • If load current exceeds 15% to 20% not observing this noise oscillation issue.
  • How can we overcome this noise issue in the light load operation?

Thanks for your support in advance.

Rgds,

Babu

  • 0
    TI__Genius 12795 points

    Babu,

    Can you please share the waveform and schematic with us?

    thanks

  • 0 in reply to Ning Tan
    Prodigy 55 points

    Hello Ning Tan,

    Following image shows reference schematic & component values used in our circuit,

    Also refer waveforms captured @ 50% scaled operational condition. Out of 8 Wfm , 4 meant for 100nF SS cap value & other 4 meant for 1uF SS Cap values, Which is highlighted in the waveform name itself.

    • CS @ IC pin-15 , COMP @ IC pin-4 (Thru 1kOhm) , SS @ IC pin-5 and Vout. 

    50% scaled operational waveform with 100nF & 1uF SS capacitor.zip

    Rgds,

    Babu

  • 0 in reply to BABU SANKARAN
    TI__Genius 12795 points

    Babu,

    We will investigate and get back to you asap. Will let you know if there is any question.

    Best,

    Ning

  • 0 in reply to Ning Tan
    TI__Expert 6150 points

    Team, please help with your feedback at the earliest.

  • 0 in reply to PRAHLAD Supeda
    TI__Genius 12795 points

    We are working on it. Please be patient.

  • 0 in reply to Ning Tan
    Prodigy 55 points

    Hello Ning,

    Did you get any thought.

  • 0 in reply to BABU SANKARAN
    TI__Guru* 86266 points

    Hello,

    Is your input voltage specification correct?  

    Can you provide a complete schematic?

    Regards,

  • 0 in reply to Mike O'
    Prodigy 55 points

    Hello Mike,

    Actual Spec: Vin - 80 to 120V  , Vout - 13.8V , Irated - 35A , Transformer TR - 4.5:1:1 , Fsw - 150kHz,  0.36V @ DCM , & Dmax considered as 0.8 @ Vin min & Vout.

    Lmag : 110uH & Llkg : Lshim + llkg = 1uH +0.5uH

    During measurement & issue observation actual operational conditions, Corresponding waveforms attached in previous thread. 

    -  35V INPUT 5 OHM LOAD

    - 45V INPUT 5 OHM LOAD 

    - 50V INPUT 5 OHM LOAD 

    - 55V INPUT 5 OHM LOAD 

    - 60V INPUT 5 OHM LOAD 

    Because of confidentiality we can not share our schematics, could you share your mail ID.

  • 0 in reply to BABU SANKARAN
    TI__Guru* 86266 points

    Hello,

    It looks like you are not using UCC28951 in a conventual phase shifted full bridge (PSFB) converter.

    A conventual phase shifted full bridge does not have an input range of negative to positive voltage range.

    Generally for a phase shifted full bridge would be typically design the input range for 3 to 1 without crossing the zero boundary.

    You could design it for positive voltage with a 3 to 1 range for positive voltage or a negative 3 to 1 input voltage range.   I would not recommend going from - to + input.  You will most likely run into issues with transformer selection and duty cycle control, especially when considering the zero voltage input boundary.

    Your design so far just seems to be for a negative input voltage range.  It appears you have it running up to 50% load and just have issues with output ripple voltage at 2.76 A or 8% load roughly.  More than likely your converter is going into light load burst mode.  The duty cycle is < tmin*fsw.  tmin is set with the Rtmin resistor. 

    It may be possible that your design does not have enough output capacitance to suppress output ripple voltage that occurs during burst mode.  The following application note has section on selecting output capacitance for a phase shifted full bridge.   This should help reduce your output ripple voltage with the negative input voltages.  https://www.ti.com/lit/pdf/slua560

    Regards,

  • 0 in reply to Mike O'
    Prodigy 55 points

    Hello ,

    Vin range is from +80Vdc to 120Vdc, We don't have negative input voltage requirement.

  • 0 in reply to BABU SANKARAN
    TI__Guru* 86266 points

    Hello,

    That is achievable.  However, I am not sure why you are testing the design at 35 to 60 V input.  If your minimum input is 80 V.  If you sized your transformer correctly you would not be able to regulate the output voltage at 35 to 60 V.  So your transformer turns ratio is not correct.  You can check that with application note SLUA560.

    My comments about burst mode and output capacitance size still hold true.  I would double check the capacitor with application note SLUA560.

    If you application is typical PFSB application you can use application note to review the design.  There is also a link to the excel design tool in the application note that uses the same equations as the application note that you can use to check the design as well.

    Regards,

  • 0 in reply to Mike O'
    Prodigy 55 points

    Hello Mike,

    Just from board bring up point of view , we thought of evaluating from low voltage first then step by step will reach to nominal operation.

    As a open loop operation with different phase shift condition under this voltage level we ensured output voltage as per voltage gain.

    As per previous thread , Test & system operational conditions : Vin +35Vdc to +60Vdc , Vout +6.6Vdc (same captured in the wfm) , Rload 5 ohm.

  • 0 in reply to BABU SANKARAN
    TI__Guru* 86266 points

    Hello,

    Your inquiry is under review and I will get back to you shortly.

    Regards,

  • 0 in reply to Mike O'
    TI__Guru* 86266 points

    Hello,

    It is O.K. to test your design at lower input voltages.  It also makes sense the design could not regulate the full output voltage of 13.8 V.  It sounds like you adjusted the feedback to maintain the 6.6 V output. 

    With this new output level you are seeing excessive ripple voltage at light load.

    My comments about burst mode and output capacitance size still hold true.  I would double check the capacitor with application note SLUA560.

    If you application is typical PFSB application you can use application note to review the design.  There is also a link to the excel design tool in the application note that uses the same equations as the application note that you can use to check the design as well.

    Since I am supporting you on another thread that you keep referring to, to reduce confusion, I am going to close this thread.  We will continue the correspondence on the other thread.

    Regards,