UCC28951: Ringing on PSFB Secondary and primary

Dean,

Can you overlay the ABCDEF signal in one screenshot, especially at different nodes (IC out, isolator out, half bridge driver out)?

I'd start with no/little load first to ensure the waveforms are expected. 

Best,

Ning

Hmm, I only have a 2 channel scope so I think what you're asking for is difficult for me to perform.  I think we can disregard outputs E, F for now as the synchronous fets are not driven at low loads?  If I common the primary and secondary (currently isolated) I might be able to do each output A, B, C, D at different nodes on one page (with IC out signal on channel 1 trigger for all shots).  Would that help to ensure waveforms are as expected?

You can focus on the ABCD for now but I strongly suggest to have a 4 channel scope to capture the waveforms. 

Hi Ning, please find attached scope signals.  I have done my best to make it as clear as possible.  All signals look correct to me but I would appreciate if you could take a look.  Sorry I don't have access to 4CH scope at this stage.

JQ102-ScopeSignals20240626.pdf

Dean,

The control signal timing seems to be OK, although you need to double check if the duty cycle is what you expect.

The actual gate signal is quite different from the IC signal, as can be seen below. Are you expecting >200ns delay here? What about SR side? I'd recommend to check the timing for all ABCDEF at the gate node and see if there is any issue.

Also, the gate voltage ringing in the middle of cycle must come from something else. The IC signal is fairly clean. You need to check your signal path from IC to the FET gate to isolate the source.

Best,

Ning

Hi Ning,
Thanks for your assistance.

Regarding the 200nS delay.  From IC signal to gate we have the 12V to 5V resistive divider, then the ISO7240CF isolator, then the UCC27714 gate driver.
Measure delay through the resistive divider and ISO7240:

Around 65nS.  I improved that a bit by dropping the R28, R36 resistive divider from 15K-10K to 1K5-1K0.

So from 65ns to 45nS.  According to ISO7240CF datasheet that's around what is expected:

Regarding the gate voltage ringing in middle of cycle:

And from UCC27714 gate driver Pin 1 to Mosfet gate we have:

About 96nS.  According to datasheet its 90-125nS so we're in the ballpark.

96nS + 46nS = 142nS so it's in the ballpark.  Does this need to be improved?  I believe I found the ISO7240CF isolator UCC27714 gate driver solution from one of the TI app notes.

Regarding the gate voltage ringing.  I don't think it is from signal path from IC to the FET gate, I think it is mirrored from what is on the source of the high side fet.  It is much worse until I added all the RC snubbers which is part of my original questions (why the need for all the snubbers in my circuit not seen on app notes).
This is high side fet Q2 Ch1-S, Ch2-G with no snubbers-a lot worse.

It lines up with the turn off of opposite high side fet.

Ch1 Q1S Ch2 Q2-G.

---------

The SR side is not switching, this is very light load 1A so I am not expecting any switching at these light load because CS is below DCM threshold.

Thanks for your assistance.  I'm getting really frustrated with all the noise on this circuit and really need help to progress any further.

I echo your frustration and I wish it was a simple issue that we can figure out by few threads exchanges. 

The delay may match your calculation but you can also notice that the turn on and off are not fast. This is likely due to your resistor divider that acts like a low pass filter because of all the parasitic. We haven't reviewed your layout yet so we don't know if there is any coupling between different nodes for the ringing.

At this point, I'd recommend to have some live discussion with experts to analyze your design. Also, having 2 probes only really limits your efficiency here. Please ask your company to sponsor the right equipment. 

Thanks

Hi Ning,

Sorry, I didn't mean to suggest I was frustrated with your support, just the design in general.

Where you say "turn on and off are not fast" are you referring to the signals at the gate:

Like the CH2 Blue signal above.
 If it's the gate signal with slow rise/fall time you are referring to there is currently a 3R0 gate resistors R5, R6, R10, R11, I could perhaps investigate lowering that?

If we're out of suggestions on the forum perhaps a live discussion with experts could help.  How would we set that up?

I am investigating getting a 4channel scope but may take some time to sort out.

Thanks,
Regards,

Dean.

Dean,

Understand. I know you are not suggesting the frustration on our support.

Yes, you are showing to the right waveform I was referring to. The fall time is equivalent to the deadtime already. You want to limit the rise/fall time as short as possible to improve the efficiency.

I don't know why you have to use a divider to drive the FET. The FET Vgs is rated at 20V based on the datasheet. UCC27714 output ranges from 10 to 18V. You could apply direct drive.

Another suggestion, you can add the RDR circuit (for each FET) to damping the ringing while maintaining the fast rise/fall time. You can fine tune the value based on the measurement. Generally, the R1 is few ohm, R2 is slightly smaller than R1. R3 can be kilo ohm.

Please contact TI sales team first to set up a proper channel for support. If you don't have an assigned contact, you can leave your email here and we will try our best to support.

Ning

Hi Ning,

Thanks for your response.
I think you misunderstand, as per my circuit diagram I am not using a divider to drive the fet.  the divider I was referring to is between the UCC28951 (which runs on 12VDC on the isolated secondary and the ISO7240CF isolator which runs on 5VDC.

The FETS are driven from the UCC27714D via 3R0 gate resistor and 10K pull down resistor.

So, if it's slow I don't understand why, I'll investigate more in the morning.
FYI, here is my schematic which should have been included in my original post.
JQ102A+Mods-SchDoc1.pdf

My email is dean@designelectronics.com.au

I don't think I have an assigned contact, the devices for the prototypes were purchased through Digikey.

Thanks,
Dean. 

Thanks for the clarification. 

The waveform of the isolator output to the HB driver input (CH2) is fairly clean. 

From the input of the HB driver to Vgs, there is a big difference. 

I suggest you to focus on the circuit below.  The Ciss is 15nF, R5 is 3 ohm. The time constant alone is 45ns. You may want to reduce R5.

Noise may be a separate issue and it is better to have at least 4 probes to debug it.

Ning 

Hi Ning,
Thanks for your response.  I did change the gate resistors to 1ohm as suggested without much effect.
Today I checked everything around the UCC27714 and I think everything is behaving as expected.
If you look closely at the signal below:

Ch1 is UCC27714D - Pin 1 Input.  Ch 2 is UCC27714D Pin 12 - Output to high side fet gate.
It looks like really slow fall time right?  But actually the UCC27714D signal does not switch to ground to turn the high side mosfet off, it just needs to switch Mosfet VGS to zero volts (see below).

It switches HO to HS, not to ground volts.
So I think the high side mosfet is actually switched off within 100nS of the UCC27714D input going low.  You can see the little step in the blue trace above.  100ns is actually in spec for the propagation delay UCC27714D tPDHL.

So although the negative edge of the gate waveform looks slow in this view I don't think it's bad in reality.
If it were then the difference signal here driving the transformer would not be correct.

Unless you have more things you want me to try, can you advise if we can progress this to some live discussion with experts to analyze my design as you suggested earlier?

Thanks,
Regards,

Dean.

Dean,

Let's communicate via email.

Best,

Ning

Hello Dean,

I am taken this over from Ning.  I reviewed your original questions and it looks like you are concerned about the ringing on the ringing on the SR FETs.

1.  You can snub the ringing across the SRs with and RC snubber directly across them.  The following link will bring you to an application note that has a section on how to setup an RC snubber across output rectifiers.  I know the application note is written for flyback converters.  However, the calculations for setting up a snubber across a secondary rectifier are very similar to that of a PSFB converter. 

https://www.ti.com/lit/an/sluaac5/sluaac5.pdf

2.  If you are concerned with the level of the voltage spike across the SR.  You might consider using a traditional RCD clamp.  The following thread discusses how set this up.   The EVM and the excel tool use a special clamp that was used to try to recovery the leakage energy.  I found the RCD clamp to be easier to use and more efficient.  The following thread discusses this as well.

https://e2e.ti.com/support/power-management-group/power-management/f/power-management-forum/1132532/ucc28950-ucc28950-senkron-rectf-snubber-question

3. One last thing you also want to make sure the SRs turnoff before inductor critical conduction.  You need to do this to prevent negative current going through the FETs and causing excessive voltage spikes at FET turnoff.  This can be done by properly setting up the DCM comparator.

The following link will bring you to an application note that goes through the step by step design process of a PSFB using the UCC28951.  There is a section on how to setup the DCM comparator. 

https://www.ti.com/lit/pdf/slua560

Regards,

Mike

Hi Mike,

Thank you for taking a look at my enquiry.

Yes, I was/am concerned about the ringing on the SR FETs at light loads which increases as the load is increased and was causing excessive heating of the RCD resistor.

This is the ringing seen on the SR Fets with no RC snubbers and no RCD snubber.

Ch1 – Q7D-S, Ch2 – Q8D-S.  Vout is 47.7V @ 4A, Vin is 60V.

So, as per your suggestion (1) I added RC snubbers directly across the SR’s Q7 & Q8. After lots of trial and error I came up with 5nF + 0R39.

Still significant ringing but amplitude and frequency much reduced. Is this typical or acceptable?  That's about the best I could get it.
Keep in mind I am only testing at very light load of 4A, so even well below DCM threshold of 30% maximum load.  So the SR are not switching yet, it is only using the body diodes of the FETs.  I’m hoping to get to maximum load of around 90A.

I then tried your suggestion (2) of RCD snubber.

First calculated resistor using formula from…

R8 = VDSmax * 0.8 – VD6 – VoutX2/IL1 Max.

Vds Max for IPW60R041P6 is 600V IoutMax IL1Max is 90A.

600V * 0.8 – 0.8V – 48V*2/90A

480V – 0.8V – 96V/90A

383.4V/90A = 4.26 Ohm.

I tried that in this configuration (without using the 5nF + 0R39 RC snubber) with R8=5R6:

Didn’t seem to have any effect, did I calculate things correctly?

I also tried the original snubber configuration:

The resistor R2+R3 1K2 3W gets very hot:

So, it is/was effective in reducing the ringing but R3 gets unacceptably hot and efficiency greatly reduced.

Regarding your suggestion (3), as I mentioned above, load is currently well below DCM threshold so SR fets not triggered yet.

I was also experiencing high voltage ringing on the primary side FETs as well.

--------------------------------------------

I was also experiencing high voltage ringing on the primary side FETs as well.

Ch1 – Q3 D-S.  Ch2 Q4-D-S.

I found adding extra bulk capacitance across the rail closer to the fets improved this significantly.

But I’m getting the double switching on the lagging side.  I checked everything on that side with the UCC27714D Hi-Lo side fet drivers but everything looked ok.  Can you advise what might be causing that double switching on the blue trace?

I added R-C snubbers across all four primary fets. 1R0-10nF across low side fets, 5nf 6R0 across high side fets.

Some improvement but double switch on lagging side (blue channel) still evident.

I also noticed output voltage is just starting to drop out with light load of 4A output drops from 47.8V to 46V.  That is with 60V input so that’s worrying me as well because webench circuit I based my design on was down to 55V input.

So that’s where I’m at so far.  Unless you have more suggestions/comments I now intend to test with increased input voltage and output current.  That requires changing from bench PSU to batteries.

Any assistance at all you can provide would be greatly appreciated.

Thanks,

Dean.

Hello,

Your inquiry has been received and is under review.

Regards,

Hello,

Please see my comments below.

Yes, I was/am concerned about the ringing on the SR FETs at light loads which increases as the load is increased and was causing excessive heating of the RCD resistor.

This is the ringing seen on the SR Fets with no RC snubbers and no RCD snubber.

Ch1 – Q7D-S, Ch2 – Q8D-S.  Vout is 47.7V @ 4A, Vin is 60V.

So, as per your suggestion (1) I added RC snubbers directly across the SR’s Q7 & Q8. After lots of trial and error I came up with 5nF + 0R39.

> This waveform looks like you added too much capacitance.  This slowed down the ring frequency (fr).  

> fr = 1/(2*3.14*(L*C)^0.5)

> The L in your high frequency ringing from the first wave form is most likely the transformer leakage inductance + 10 nH/in trace inductance.

> You solve the fr equation for C.

When setting the snubber you set the snubber resistor (Rs) first to dampen the ringing.  You set Q in the following equation to 1 and solve for C.

> Rs =(1/Q)*(L/C)^0.5 

> Once you have R for the snubber you set the snubber C (Cs).

> Cs = (0.02/fsw)*1/(3*R)

Still significant ringing but amplitude and frequency much reduced. Is this typical or acceptable?  That's about the best I could get it.
Keep in mind I am only testing at very light load of 4A, so even well below DCM threshold of 30% maximum load.  So the SR are not switching yet, it is only using the body diodes of the FETs.  I’m hoping to get to maximum load of around 90A.

>Increasing R should dampen the ringing amplitude.

>Your layout traces may be too long.   Consider changing the layout and shortening the trace length.

I then tried your suggestion (2) of RCD snubber.

> This is an RCD clamp and only will clamp the peak amplitude of the ring.  It is will not dampen the ring frequency.

> To reduce the heating of the the clamp resistor the more traditional RCD clamp was recommended.  

First calculated resistor using formula from…

R8 = VDSmax * 0.8 – VD6 – VoutX2/IL1 Max.

Vds Max for IPW60R041P6 is 600V IoutMax IL1Max is 90A.

600V * 0.8 – 0.8V – 48V*2/90A

480V – 0.8V – 96V/90A

383.4V/90A = 4.26 Ohm.

I tried that in this configuration (without using the 5nF + 0R39 RC snubber) with R8=5R6:

Didn’t seem to have any effect, did I calculate things correctly?

> This is an RCD clamp and only will clamp the peak amplitude of the ring.  It is will not dampen the ring frequency.

I also tried the original snubber configuration:

> This is an RCD clamp and only will clamp the peak amplitude of the ring.  It is will not dampen the ring frequency.

The resistor R2+R3 1K2 3W gets very hot:

>It was found that the RCD with R3 tied to the output will get hot because this resistor conducts for a long time.

>This why I suggested the more traditional clamp.  The thread previously mentioned has calculations for setting this up. 

So, it is/was effective in reducing the ringing but R3 gets unacceptably hot and efficiency greatly reduced.

>It was found that the RCD with R3 tied to the output will get hot because this resistor conducts for a long time.

>This why I suggested the more traditional clamp.  The thread previously mentioned has calculations for setting this up. 

Regarding your suggestion (3), as I mentioned above, load is currently well below DCM threshold so SR fets not triggered yet.

>This is good.  So there is not reverse current in the FETs.  This will protect them in the design.

I was also experiencing high voltage ringing on the primary side FETs as well.

Ch1 – Q3 D-S.  Ch2 Q4-D-S.

I found adding extra bulk capacitance across the rail closer to the fets improved this significantly.

> Your trace length in your design may be considerably long.  Consider relaying out the boards and shortening the traces.  10 nH of inductance is added for every inch of trace.

> There are recommendations in the UCC28951 data sheet for layout that you might find helpful in section 10 of the data sheet.

> The following link will bring you to a 300 W reference design that was designed to use the UCC28950 and UCC28951 in a phase shifted full bridge.  There is a schematic, layout and test data in the user's guide at this link.  You might want to study the layout it may give you ideas on how to improve your layout and reduce ringing in your design.

https://www.ti.com/lit/ug/sluub02a/sluub02a.pdf

But I’m getting the double switching on the lagging side.  I checked everything on that side with the UCC27714D Hi-Lo side fet drivers but everything looked ok.  Can you advise what might be causing that double switching on the blue trace?

I added R-C snubbers across all four primary fets. 1R0-10nF across low side fets, 5nf 6R0 across high side fets.

Some improvement but double switch on lagging side (blue channel) still evident.

>I believe you are talking about the resonant ring of the switch node.  I have circled it below.

>To fix this you just need to adjust RDELAB/CD to turn on the FETs to valley switch.

>The following link will bring you to an application note that goes through the step by step design process of the UCC28951 in a phase shifted full bridge.  It gives recommendations on how to setup the timing the turn on delays to give valley switching at light loads.

https://www.ti.com/lit/pdf/slua560

I also noticed output voltage is just starting to drop out with light load of 4A output drops from 47.8V to 46V.  That is with 60V input so that’s worrying me as well because webench circuit I based my design on was down to 55V input.

>If the output is dropping out it may be going into and over current fault due to noise on the CS pin.  You might want to check that.

So that’s where I’m at so far.  Unless you have more suggestions/comments I now intend to test with increased input voltage and output current.  That requires changing from bench PSU to batteries.

Any assistance at all you can provide would be greatly appreciated.