Other Parts Discussed in Thread: PEET-GUI
Tool/software:
I would like to know the minimum ON time(typ and max) for the step-down DCDC.
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi Sato,
Typical rise/fall time of is around 1.5ns, but please note that it also depends on the PCB parasitics of the SW-node, but this is a typical value.
For efficiency calculations you can use our tool: https://www.ti.com/tool/PEET-GUI.
Thanks,
Field
Could you also tell me the minimum off time (type and maximum) of the step-down DC-DC?
I would like to use formulas 12 and 13 from Application Report "SLVA477B" (Basic Calculation of a BuckConverter's PowerStage), but are the ripples in these formulas peak-to-peak values?
Hi Sato,
formulas 12 and 13
In section 8.2.1.3 on page 64 of the datasheet linked here, has the recommended output capacitance values. You can search online to find values of ESR for capacitors as desired. We also have a PSpice model available on TI.com to test for selected values or designs. But using the PEET-GUI above, you should be able to find the efficiency as desired and calculate from there. Or you can select a capacitance value or multiples of these and rearrange the equation to solve for your desired variable.
Thanks,
Field
Hi Sato,
Due to the holiday in the US today, I will hope to get you information tomorrow or early next week since most of the experts are currently out of office.
Thanks,
Field
Hi Sato,
I do not have this information available from our documentation. Can you use the Pspice model from the product folder (https://www.ti.com/product/LP8732-Q1#design-tools-simulation ) to get what you need?
Regards,
Matt