UCC28750: Full load startup issues

Hi Himanshu,

Thank you for reaching out.

Yes it is possible to hit over power threshold because, FB is maxed out and if duty is greater than 60% and the FB signal mostlikely higher than OPPP ramp it can trigger OPP. going into hiccup mode.

The UCC28750 should be designed so that CS pin is designed with sufficient headroom as mentioned in the datasheet allowing for sufficient margin for transients/ startup currents.

Regards,

Harish

Hello Harish,

Thank you for the quick response. In the datasheet the headroom mentioned is only 20%.

I tried reducing the value to 1.8 ohms still im observing the same issue. If there is anything else im missing please guide me.

I have a taken a trial with 1.5 Ohms as current sense resistor. My observation are as below:

waveforms for reference. Green Waveform : Across Rcs, Yellow waveform = after slope compensation resistor (Across the 56pF cap).

...

Slope compensation resistor = 1k, capacitor = 56pF.

I have observed one more issue. I'm not able to use over voltage protection. I have connected 3 resistors of 1.5 Mega in series with a 47k resistor for overvoltage fault detection across the 47k, (it should read around 4 volts @ 270 vac input). But as per my observation the fault pin is somehow clamped to 2.45 volts and the voltage is not varying irrespective of the applied input voltage.

Hi Himanshu,

Thank you for the reply.

It looks like from the waveform, Vcs hits greater than 900mv and if this happens for 8 switching cycles during startup, the IC will trigger shutdown. The effect will be more as the voltage is increased with increasing load.

I think is what is happening in your case.

Regards,

Harish

Is there a way to reduce that spike? Because Coss and other parasitics are beyond our control. 

The only way could be to put capacitor as close as possible to the CS pin, maybe directly across the pins 1 and 4 and try values from 22pf upto 200pf to see if this helps.