LM74704-Q1: Question for specification of FET good and parallel LM74704-Q1 configuration instead of diode OR application

Hi Kazuki,

Thanks for reaching out. I will get back to you by tomorrow.

Regards,

Shiven Dhir

Hi Kazuki,

1. Yes, FETG remains high as it only sense VA-VC.

2. Yes, it will fall in this case as VCAP should be greater than VCAP_UVLO.

3. This can happen actually. Some controller may trigger false FET_SHORT. I will check on this and revert.

Regards,

Shiven Dhir

Hi Shiven-san,

Could you please answer following remained quetion?

Does EC table's FET GOOD HIGH include voltage drop at RFETGOOD or we should add voltage drop at RFETGOOD to estimate actual FET good pin output voltage?

Also, I'm waiting your update regarding 3..

Best regards,
Kazuki Kuramochi

Hi Kazuki,

Hope you are referring to this spec.

This is for LM74703-Q1 which has push/pull output from FETG which doesn't need any resistor.

For LM74704-Q1, voltage depends on the external voltage used.

Regarding #3, yes during, FETG pin might not be dependable.

Regards,

Shiven Dhir

Hi Shiven,

I understand there is the rating but this chart also have pull-up and pull-down resistor for LM74703-Q1 as 50kohm.
Then, could you please tell me which is LM74703-Q1's push-pull output stage configuration?

If left side is used LM74703-Q1, there is output current limitation and output voltage should depend on output current.
So, I'm asking about RFET_GOOD.

Regarding #3, Could you please tell me about variation information delay between EN=HIGH to start monitoring FETGOOD and starting monitoring FET good to gate turn on?
I can find the delay from EN=High to gate turn on at datasheet but I cannot found those information.

Best regards,
Kazuki Kuramochi

Hi Kazuki,

It is the left one.

Regarding #3, ill check and confirm.

Regards,

Shiven Dhir

Hi Shiven-san,

I understand that FETGOOD configuration is left.

Based on this answer, could you please provide output current value when you define FETGOOD HIGH?
As I asked, PU/PD cause voltage drop depends on output current so this information should be at FETGOOD HIGH rating.
FETGOOD output current rating is 1mA so voltage drop will be 50V at worst case...
Or does this FETGOOD HIGH mean supply voltage for PU resistor?

Also, I'm looking forward to hearing back from you regarding #3 as well.

Best regards,
Kazuki Kuramochi

Hi Kazuki,

FETG current rating stated as 1mA is the current flowing into the pin and is meant for LM74704-Q1.  FETG HIGH means the voltage at this node.

Regarding #3 FETG monitoring comes into action only VCAP> VCAP_UVLO. Hence in EN low to high transition, until VCAP reaches VCAP_UVLO, circuit wont monitor FET status. FETG short detection only happens at once instance and that is when VCAP is at 6.6V. Hence EN timing will not alter this feature as that can mismatch by only some of uS and VCAP to reach VCAP_UVLO will take ms.

Regards,

Shiven Dhir

HI Shiven,

If FETG HIGH means the voltage at output node, the voltage include voltage drop from high side resistor.

As you can see below, HIGH condition's current frow is red arrow.

It mean blue marked point voltage should be supply voltage minus voltage drop at yellow marked resistor(50k ohm * red arrow current).
So I'm asking you about the current condition when you define FETG_HIGH condition.
Could you answer my question?

Best regards,
Kazuki Kuramochi

Hi Shlven-san,

I understand that the FETG high voltage is rated at non load condition.

By they way, we have additional question regarding FET short detection.
At previous discussion, you said some LM74704-Q1 may wrong FET short detection at start-up.
So customer confirmed FET short detection behavior using EVM.
At this confirmation, they used only one EVM(non-series configuration) to confirm this device's behavior.

Their observed behavior is as below.

1. They apply revere voltage on LM74704-Q1 EVM during EN=low.(Vin=12V/Vout=13V)
2. They toggle EN to High.
3. FET Good pin become low and GATE pin become same voltage as Anode pin.(we think it detect Short event due to Vac is lower than 200mV(approx. -1V))
4. They decreasing Vout voltage to 8V.
5. FET turned on but FET Good pin maintain low.

Our expected behavior is FET Good pin release low condition when reverse voltage event is released.
This is because we think FET Good pin won't be reliable if reverse voltage happen during turn-on in parallel application.

Then, could you please answer following questions?

1. Is their observed behavior anticipated?
2. Will FET short event during start-up latch FET good to Low?
3. Is there any way to resolve miss detection of FET short in customer application(Parallel LM74704-Q1/Using same EN signal, Output is shorted as OR application)?

Best regards,
Kazuki Kuramochi

Hi Kazuki,

You mentioned that reverse voltage was applied. But Values are (VIN =12 VOUT = 13V), did you mean VIN = -12V?

Looks like you are trying reverse voltage protection in ORING configuration.

When you powered EN while VIN was negative, did FETG switch from high to low? Can you share waveforms to analyze it?

Ideally FETG to make any decisions, it requires voltage across VCAP+ and VCAP- to be around 6.6V and with VIN negative, charge pump cannot go high.

1. I am not clear on your case, but FETG low in ORing is anticipated.

2. Yes, FETG short at startup will latch FETG to low.

3. There is no way to resolve miss detection of FET short in ORing. It is device's behavior.

Regards,

Shiven Dhir

Hi Shiven,

Their test case is Vin is 12V and Vout is 13V.

In parallel ORing application, they anticipate that the reverse voltage may happen if any one LM74704-Q1 input has higher voltage than other inputs.

We don't have waveform and they just made matrix as what event happen at FETG pin during some VIN/VOUT/EN pin status conbination.

In the ORing configuration of the LM74704-Q1, I understand that the FETG pin would remain low as latch, except for the LM74701-Q1, where FET short-circuit detection was first performed.

However, customer still want to use FETGOOD function and they may change device from LM74704-Q1 to other device if FETGOOD won't work in their use case.
Is there any way to use FETGOOD function including adding external components or circuit?
For example, adding gate resistor may be able to avoid miss detection of short detection.
This is because this scenario won't happen if all device completed short detection before fully conducting FET at all devices.(I understand this solution have some cons...)

Best regards,
Kazuki Kuramochi

Hi Kazuki,

Let me think of a way if any. I will get back to you by tomorrow.

Regards,

Shiven Dhir

Hi Kazuki,

FET short is detected by monitoring the drop across VANODE and VCATHODE. During ORING, this will be very low. This is device's behavior. 

We cannot avoid FETG detecting short in ORING.

Regards,

Shiven Dhir 

Hi Shiven-san,

Thank you for your consideration.
I understand.

Best regards,
Kazuki Kuramochi