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TPS3851-Q1: confirmation about the reset timeout period (tRST) in WDO pin

johnny fu
Prodigy 10 points
Part Number: TPS3851-Q1
Other Parts Discussed in Thread: TPS3851

Tool/software:

Hi TI experts

I have a question shown as below.

The WDO tRST is only about 100us used in our product as shown in the figure (blue curve), and the WDO pin is connected to our company's SOC. But in another test, the WDO tRST is about 2ms when the WDO pin is connected to an FPGA produced by Xilinx. So I wonder whether  the WDO tRST is decided by the load (the SOC system). The typical WDO tRST shown in the datasheet is just the maximum reset timeout period that the chip can support? I do not know whether the WDO tRST is 100us is reasonable because it is different from the datasheet. Thank you!

  • 0
    TI__Expert 5660 points

    Hi Johnny, 

    Thanks for your question!

    It is generally unusual if the device behavior is depending on the load. Can you please share a schematic if you think you need further assistance?

    The reset timeout period ,trst,  that is highlighted in below is defined as typical 200 ms.

    Please find my bench data in below also.

    I hope this helps!

    Best Regards,

    Sila 

  • 0 in reply to Sila Atalar
    Prodigy 10 points

    Hi Sila

    The connection between TPS3851 and SOC is shown as below. My test data is the same as yours when the WDO pin is not connected with the SOC reset pin. But there is a problem when WDO pin is connected to the SOC reset pin. When the WDI signal is not normal, the WDO signal will become low level, so the SOC will be reset, then the SET1 pin will be set to low level and TPS3851 will be disable. Therefore, the WDO pin will be pulled up to 3.3V by pull up resistor and then SOC reset pin will be set to high level.

    The time from SOC reset pin becomes low state to SET1 pin becomes low state is usually faster than 200ms.

    Personlly, the TPS3851 will be disabled very fast when the SOC reset pin be set to low state is the reason why reset tiemout peroid tRST is so short.

    Is it correct? Thank you.

  • +1 in reply to johnny fu
    TI__Expert 5660 points

    Hi Johnny,

    I see, it is not only depending on the load but in your case your are disabling the device as well. 

    Yes, then it normal that you are seeing a shorter delay than 200 ms. The reset timeout period is defined 200 ms when VDD is higher than threshold and MR pin is High.

    Please find my bench data in below. If you are disabling the device while there is a WDO assertion, the device will prioritize the Set pin and pull the WDO output high immediately. 

    Best Regards,

    Sila