Tool/software:
Hi team,
I have one question on TPS4800-Q1.
The FLT_GD is described as UVLO of gate drive, why it is asserted when PU to SRC is above 7.5V, instead of below 7.5V?
BR,
Xiaoying
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Tool/software:
Hi team,
I have one question on TPS4800-Q1.
The FLT_GD is described as UVLO of gate drive, why it is asserted when PU to SRC is above 7.5V, instead of below 7.5V?
BR,
Xiaoying