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TPSM53603: TPSM53603RDAR power interruption calculations

Part Number: TPSM53603

Tool/software:

I am using 2 no.s of TPSM53603RDAR for generating 5V and 3.3V. The input is 12V DC. I have a power interruption requirement of 20ms on my device and I am planning to use a capacitor bank after 12V output, as an input to both the TPSM53603. I need some help with the calculations that should be done. Should I consider TPSM53603's efficiency while calculating the hold up capacitor value? Can you help me with the calculations?

Also, if I add a high value cap (say 2200uF) on the output 3.3V, is that going to affect the output? Is it recommended to have decoupling caps this big if I have some high consumption load just on the 3.3V line (about 1.5A) and not on the 5V line? How do I calculate the required decoupling capacitor values?

  • Hello,

    Do you have a schematic which you can share?

    Best regards,

    Ridge

  • Power interruption capacitor calculations, placed after a 12V DC-DC converter - then fed to 2 x TPSM53603 which converts to 3.3V and 5V. the total load on 12V DC-DC is 550mA. Is it right to calculate the capacitor voltage after time t and estimating if the voltage is greater than the required voltage. I would like to share my calculations.

    Vcc (V) 11.5
    Normal Current (A) 0.55
    Min Required Vtg (V) 6.2
    Min Required I (A) at vtg 6.2 0
    C (uF) 1800
    Time (ms) 15
    EqZ (ohm) 20.90909091
    Tau 0.03763636364
    EqVtg of Cap after T (ms) : 15 7.7199
    Eq Discharge Current of cap after T (ms) : 15 0.3692

    Or, is it right to use the energy calculations for a capacitor.

    Which efficiency parameter is to be considered if I am using 2 x TPSM53603. Of TPSM or my 12V DC-DC converter used before TPSM

    TPSM53603
    Hold-up time 15 ms
    Output power of converter 6.325 W
    DC-DC efficiency 0.86
    VH 11.5 V
    VL 6.2 V
    C hold-up = 2 * P out * t / Eff * (V² cap - UVLO²), 2351.983103 uF

    I am not able to understand how to proceed. Sharing a snip below. I understand that this may not be the best way to deal with interruption. But is there a way to make things calculated and better in this existing design?

    a. 12V DC-DC converter output. 11.5V because the schottky diode drops about 0.5V

    b. 3.3V using TPSM53603RDAR. Load around 1.5A. Is this 2200uF really helpful and needed? Does power interruption work if capacitors are placed on 3.3V or 5V rails?

    c. 5V using TPSM53603RDAR

  • Hello,

    I don't think putting the large capacitors on the output of the buck converters will help if the goal is to maintain the input voltage. 

    It looks like you are on the right track for the capacitance calculation, but it is difficult to estimate the fact that the output current of the capacitor will change as the capacitor is discharged. Make sure to follow i=c*dv/dt. Also keep in mind that your efficiencies will likely be different for the different output current and voltages you have setup on the two converters. I recommend using similar data found in the datasheet for the efficiency estimation. 

    Have you tried simulating this with 2200uF yet? 

    Best regards,

    Ridge

  • Yes. I tried Ridge.

    1. With 2200uF

    2. Recommended 47uF

    Warning before simulation was this

    If we do not place 2200uF here, but have one near to one of our high power consuming chips, will it be fine?

  • Hello,

    Having too large output of an capacitance on the buck converter can cause instability. 2200uF of output capacitance is too much for the TPSM53603 devices. I cannot comment on how it will impact devices at the point of load.

    Best regards,

    Ridge

  • Okay. Thanks Ridge. Will take care of that.

    So, if I want my capacitor to discharge above 6V in 20ms considering Vout+1 threshold of TPSM53603, what is the correct way to estimate the Hold up capacitor value? I have 2 x TPSM53603 each giving out 3.3V and 5V. Let's consider the minimum UVLO as 6V for 5V output TPSM.

    A. If I calculate according to C hold-up = 2 * P out * t / Eff * (V² cap - UVLO²), and if I calculate voltage of a capacitor with lesser capacitance than C hold-up value, that it discharges to after time t, it still is greater than the UVLO value. What seems the right way to calculate the capacitance value?

    B. Also, can you shed some more light on this: It looks like you are on the right track for the capacitance calculation, but it is difficult to estimate the fact that the output current of the capacitor will change as the capacitor is discharged. Make sure to follow i=c*dv/dt. 

    I want to know how will the capacitor be able to provide the load current if it is decaying?

  • Hello,

    Your equation looks correct. You would integrate the the capacitor equation for your timing and input, which you've already done. It looks like you are sizing the capacitor correctly. 

    The capacitor provides the current by i=cdv/dt. Again, your equation looks right.

    Best regards,

    Ridge

  • Okay Ridge. 

    May seem basic, but is there any justification on how capacitor discharges but acts as hold-up, and how is the capacitor current not affecting the connected load, as discharged current is always less than the load connected? Should it be calculated in terms of energy?

  • Hello,

    For all buck converters, the input current can be calculated from the total power in and the total power out: Vin*Iin*efficiency= Vout*iout

    Since buck converters are step-down converters, the input current will be less than the load current. Your capacitor equation looks right where you are calculating with the total input current of the buck converters in mind with respect to the change in time and voltage. 

    Best regards,

    Ridge

  • Hello,

    Since we have not heard from you in a while, I will be closing this thread. If you have more questions, you can create a new thread or re-open this one by replying.

    Best regards,

    Ridge