This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TL7733B: TL7733B deviation in designed time delay and measured time delay

Part Number: TL7733B

Tool/software:

Hello,

We have issue while using TL7733B, we desinged it for td= 2.6ms. see the schemaric above.

However, when we measured the delay(td) on DSO we geting around 1.8ms. 

Positive threshold voltage (VIT+) we have considered as 3V to start the measurement of delay. see the below image.

Can you please tell us why there is difference in the calculated value(2.6ms) and capture value (1.8ms)?

Are we doing measurment in right way ?