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TPS65219: Parallel LDO channels for higher current capacity

Valentin Stümpert
Prodigy 40 points
Part Number: TPS65219

Tool/software:

Hello E2E forum.

We are in need of an extremely compact power solution for a space-constrained FPGA power delivery stage.

For this, we require ~800mA of current through an LDO*(see below for asterisk). Having a separate LDO is undesirable due to the aforementioned space constraints.

We have identified the TPS65219 as our most likely target part, also due it its high configurability in terms of voltage and startup sequence via the I2C.

Our critical question is now, if it is possible to combine the output of LDO1 and LDO2 to yield the required 800mA of current?

Should this not be possible, are there any other TI products that may fit our requirements?

  • Voltage rails:
    • Input: 3.3V
    • Outputs:
      • 1.8V, 1.5A via DCDC
      • 1.2V, 2A via DCDC
      • 0.85V, 2.5A(preferably 3A) via DCDC
      • 1.8V, 0.1A via LDO*
      • 0.9V, 800mA via LDO*
      • 3.3V, <250mA via Load Switch
  • Configurability:
    • NVM for Voltage settings
    • NVM for Start up and shut down
      • Highly granular configurations like the ones possible with the TPS65219 are prefered
    • I2C interface
  • Size:
    • maximum dimensions of 7mm x 7mm
    • desirable maximum height of 1mm

* Instead of LDOs, we could also use DCDCs here, if their output ripple is less than 10mVpp

Thank you, and kind regards,

Valentin Stümpert

  • 0
    TI__Guru* 81034 points

    Hi Valentin,

    It is not recommended to combine LDO outputs. I will ask the device expert to help identify the best option we have to meet these requirements, so hopefully you will receive a reply tomorrow 6/28.

    Best regards,

    Matt

  • +1 in reply to Matt Sunna
    TI__Mastermind 22206 points

    Hi Valentin,

    Thank You for using E2E. Based on the requirements described in your message, TPS65219 seems to be the best fit. This PMIC comes in a small 4x4mm package and in most cases even when combined with discrete devices, it still provides a size optimized power solution. We can help create a TPS65219 NVM configuration file based on your application requirements that can be used to easily program and evaluate samples. 

    Most of the integrated LDOs in PMICs support up to 400mA-500mA. There are very small discrete devices that could be enable with one of the PMIC GPIOs to supply the 0.9V/800mA rail. Here are some examples: TLV757P (LDO), TPS62800 (small size Buck)

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    Prodigy 40 points

    Thank you Brenda for the detailed reply.

    Using the WEBENCH tool, I could find some fitting small-formfactor Bucks for the 0.9V/800mA rail, thanks to your suggestion.

    Looking at the Efficiency Estimator of the TSP65219, however, efficiency at our operating point for the 1.2V and 0.85V rails is dropping to and below 80%... Can this be improved by choosing specific components?

    Alternatively, the datasheet notes the TP65219 to have a maximum voltage ripple of 20mV. Can this be further improved with the output filter, so that we might be able to instead use the standalone Buck for one of the high-current rails instead?

    Would you be able to support me in terms of component choice here? Unfortunately, the TPS65219 seems to not be supported in WEBENCH.

  • +1 in reply to Valentin Stümpert
    TI__Mastermind 22206 points

    Hi Valentin,

    PMICs are not in WEBENCH but you could use tabs "Buck1", "Buck2", "Buck3" in the TPS65219 efficiency calculator to visualize the assumptions that were made. The "Rind" parameter can be modified based on your selected inductor. Click on "Update Curve" to update the calculated values. Internal parameters for the buck converters are optimized for 0.47uH inductor but you could lower the inductor DC resistance to improve efficiency. Selecting the right inductor could be challenging and often depends on the tradeoff of size, core material and cost. You could use the TPS65219EVM as a reference when selecting the external passive components.

    Similarly, for the output capacitance, select a component with low ESR to lower the output ripple. If your application is not space constraint, the output capacitance can also be increased without exceeding the max total capacitance (including SoC/FPGA and peripherals).

    Thanks,

    Brenda