TPS650864: TPS650864

Hi Michael,

Using a long trace to a distant sense point can result in worse transient performance close to the PMIC from my understanding. You can compensate for this by adding extra local capacitance, but a cleaner solution might be to use a short FB trace to the local capacitors while setting the output voltages a littler higher than the default. This way, the load side sees the correct voltage.

If you go with my suggestion, you can either reprogram the TPS650864x device at every power up, or you can use the user-programmable TPS650861 and go through the process to have your own defaults programmed into the part.

Remote FB is definitely possible with this PMIC, but I can't account for the physical nuances of your system so it's difficult to say how drastic the transient performance impact would be or whether the FB trace would start picking up too much noise because of trace routing. Shorter FB traces largely eliminate these concerns by reducing impact of these variables.

If you are in the prototyping phase, I would suggest adding both a long and short FB trace option. You can include a 0 Ohm resistor on both traces so that you can disconnect one trace or the other for testing and see which FB type you want to use.

Regards,

James

Hi Michael,

I think load side sensing makes more sense as well for your case. If you don't have any devices connected to the output rail closer to the chip, a slightly larger local transient on the rail shouldn't present too much of an issue, especially if you add a bit of extra local capacitance.

Unfortunately, the evaluation modules we have on hand don't have a way to test remote sensing, so I can't confirm the operation on my end empirically.

Regards,

James

Hi Michael,

This just means that you can pull CTL6 HIGH or LOW to select between two different voltages on a power rail. One voltage is the normal default value and the other voltage is the "sleep voltage" which is usually some lower voltage value. Different version of the PMIC have slightly different voltage settings but that's the general behavior.

Below is an example of the BUCK3 register setting for sleep mode enable. CTL3 can also be programmed as a sleep control pin.

Regards,

James

Hi Michael,

The TPS6508640 has internal PGOOD signals for all rails. The TPS6508640 is set up so that some rails respond to the power good of another power rail. This allows for further sequencing control because you can set up certain rails to only power up once a previous rail is ready.

This is important for LDOs if you are using a BUCK as the input source. You could set the LDO to ramp up when BUCKx reaches power good so that you never run into a situation where the LDO powers up without proper input  available.

These are digital settings that are changed in the programming registers (address 0x38). These programming registers are only listed in the TPS650861 datasheet since this is the user-programmable version.

For the TPS6508640, the register map in the datasheet will only show the normal 0x5E address registers.

Take a look at the TPS650861 datasheet register map section to see what I mean: https://www.ti.com/lit/gpn/tps650861

The TPS6508640 is a pre-programmed version so the sequencing and power good delays are already decided.

Below is an image that might help visualize the PGOOD sequencing logic. This comes from our OTP generator document that is usually used when programming the TPS650861 version.

Regards,

James

Hi Michael,

The datasheet should show which CTLx pins correspond to which output rails in the sequence. You will need to pull the CTLx pins shown in the power sequence HIGH to activate the rails. Unused CTLx pins can be shorted to GND.

For example, in Figure 8-4 of the datasheet, it is shown that CTL3 and CTL4 are the main two inputs needed to move through the power sequence (also CTL1 if necessary). In Figure 8-3 there is an example block diagram that shows how the CTL pins are connected so that CTL3 is the main sequence pin and CTL4 is automatically pulled HIGH by VCCINT_PG later in the sequence.

CTL1 is a DDR_EN pin that controls BUCK6 directly. CTL1 could be connected to one of the output rails depending on where in the sequence you want the DDR to enable. Or you could use your host device to enable DDR at some other time. Most designs I see just pull all the CTLx pins HIGH at the start of the power sequence by connecting the pull-up resistors to the LDO3P3 output and let the programmed PGOOD logic handle the sequencing / timing.

GPO outputs are either Open Drain or Push-Pull. If the GPOx in question is Open Drain then you will need a pull-up resistor to a 1.8V or 3.3V source in order to use the GPOx output. GPOx pins that are in "I2C" mode must be enabled using an I2C command. If the GPO is marked as "PG" then the GPO pin is programmed to respond to the state of one of the power rails (should be shown in the power sequence diagram). Below are some tables that show the TPS6508640 default settings:

I recommend the TPS65086x Schematic and Layout Checklist (Rev. A) if you want to know how specific pins should be handled. The only thing to note is that "unused" is from the perspective of the PMIC, not the user. Even if you don't plan to use a pin, if the PMIC is trying to use it then you need to provide the proper passive components so that no faults occur.

Regards,

James

Hi Michael,

The SLP pins can be programmed and tied to a specific BUCK. When a SLP CTLx pin is pulled HIGH the default BUCK voltage is used at the output (determined by BUCKx_VID register bit field). When the SLP pin is pulled LOW the BUCK output changes to a secondary output voltage (often set to be lower than the default voltage using the BUCKx_SLP_VID register bit field).

CTLx pins that are not used can be tied to GND. The CTLx pins are used to start the power sequence since the first power rail will not enable until the main power CTLx pin is pulled HIGH. For the TPS6508640, CTL3 should be the pin that starts the sequence. If you pull all the necessary CTLx pin HIGH at the start of the sequence, then the power sequence only needs to worry about the PGOOD logic to determine the order and timing of the rails. If the CTLx pins are not used, the PMIC will not power up.

The sequencing is documented in the power sequence diagram for each TPS65086x version (Figure 8-4 for the TPS6508640). If there is a specific part of the power sequence that doesn't make sense I can go into more detail.

Regards,

James

Hi Michael,

To answer your question about the power sequence...

1) CTL1 only controls BUCK6 and LDOA1

2) CTL5 needs to be HIGH as part of the GPO2 PGOOD requirements (along with CTL3 and CTL4). GPO2 internal PGOOD signal needs to be HIGH in order to allow VTT LDO to enable. GPO2 is programmed for I2C enable which means GPO2 won't activate its output until you enabled it through I2C. However, the internal PGOOD signal for GPO2 is independent of the I2C setting so the PGOOD of GPO2 is still used by the PMIC as part of the VTT LDO enable requirements.

3) LDOA2 and LDOA3 are not tied to a CTLx pin in the TPS6508640 version. These two rails are disabled by default and must be enabled by I2C.

4) CTL2 should be a SLP pin for BUCK6, along with CTL6. CTL2 does not influence BUCK3 or BUCK4. BUCK6 has an additional "fixed voltage" feature that activates when CTL2 and CTL6 are pulled LOW. BUCK2 also has a SLP mode voltage but only requires CTL6 to be pulled low to active SLP mode. 

5) CTL6 acts as a SLP pin as well. VTT LDO is tied to CTL3 and GPO2. Both need to be HIGH for VTT LDO to activate. GPO2 is tied to BUCK6 PGOOD so once BUCK6 ramps up, GPO2 

6) You are correct that CTL3 is the main enable pin.

This information is also documented in our TPS65086100 OTP Generator for Xilinx Zynq Ultrascale+ (TPS6508640 settings) excel sheet. This document is usually used to program a TPS65086100 (user programmable) version of the IC with the default TPS6508640 settings.

On the "Sequencing" tab you can see the settings for each rail and the PGOOD dependencies. BUCK6 and LDOA1 have incorrect PGOOD settings shown in the document but this should be updated in the future. The datasheet is the correct sequence. Otherwise, everything should be accurate in that document.

Regards,

James