TPIC6A596: TPIC6A596 is malfunction with the new FAB site DMOS6

Hi Sam,

How many failure ICs do you met? Are they from the same lot/same FAB?

Meanwhile, please also contact the local field for this question.

BR,

Hailee.

Hi Hailee,

Could you help check what's the difference for the marking 3BA4TCT and 3BA5SPT?

Thanks!

Hi Hailee:

   We produce 11 pc MB. TI TPIC6A956 uses 3pc/MB. Total use 33pc 3BA4TCT and the TPIC6A956 function fails for 11pc MB. Once we change to 3BA5SPT, the function works normally.

We asked the local FAE support and will send the failed IC to our vendor. Can you help confirm

1.Why the IC layout is different?

2. Any spec is updated after PCN?

Thank you. 

Best Regards,

Sam Lee

Hi Zoe,

I can't see the bonding wire in the abnormal IC, so it is recommended that you contact the local quality team.

BR,

Hailee.

Hi Sam, 

From my side, the main difference is bonding wire, more details need to be checked from the local field/quality team.

BR,

Hailee.

Hi Hailee,

      I don't care the wire bond or layout change, TI just needs to make sure everything in electrical characteristics are identical between 3BA4TCT and 3BA5SPT. In fact, we observed the timing difference but we don't know why. Sam will upload the waveforms for your reference.

Hi Hailee,

     Quick question. Any timing requirement between RCK rising edge and SRCK rising/falling edge?

Thanks 

Hi Hailee:

   We just find if we invert pin9 RCLK signal. The function can work. Can you help check what is the root cause? Thank you.

I type 0xaaaaaaaa to control 32 bit LED. EX:1010101010101..... turn on 16 bit LED and turn off 16bit LED

 Both waveform CH1-Ch4 are the the same measure point.

Inverted RCLK.png means we add an inverter for pin 9 RCK.

CH1: U11.pin22 SER_IN;   CH2:U11.pin10 SRCK;  CH3: U11.PIN9 RCK ;  CH4: U11.Pin15 SER_OUT

Best Regards,

Sam Lee

Hi Hailee,

     You can see tha failure waveform as below, CH3 is RCK and the rising edge is behind the last SRCK 3x SRCK at least. Question, any specific behavior of RCK is required? in the datasheet, it is high pulse but in out design it is low pulse. I think RCK is considered the rising edge only but don't care the high or low pulse, right? Any thing can I check for this issue?

Thanks  

Hi Jacky,

I am a little confuse, there are three waveforms, what's the difference between these two waveforms? and what do you mean failure? I can see the SEROUT data, please tell me your expected result. 

Many thanks!

BR,

Hailee.

Please answer in a same thread.

Please answer in a same thread.

First one is correct and you can see the the same data in SERIN and SEROUT but 8 SRCK shifts. This is old process TPIC6A596.

Second is incorrect and you can see the data in SERIN and SEROUT is mismatch. This is new process TPIC6A596.

okay, understood, there are supposed to be 4ICs in the chain, are they all from the new lot? since I can see some SER OUT data. 

In the failure waveform (senond one), only first chip is new lot other three are old lot.

Okay, please disconnect the first IC, and only do the test for the first IC, it's supposed to be no SER OUT signal. From your X-ray picture, there is no bonding wire inside which means no electrical characteristics.

if we inverted the RCK as below and it works as first chip is new lot. That means IC wire bound and layout is good. 

We also observed if we force the RCK to ground and the behavior is correct (SERIN and SEROUT is the same and 8 SRCK shifts) while first IC is new lot.

How about the output channel of the first IC? could you see the LED on in this test?

RCK to gorund then NO DOUT.

RCK is only related to the output stage, won't affect the SER OUT, please also measure the SRCLR signal when you do these tests.

SRCLR is always high in our design.

since your X-ray of the new lot IC is abnormal, I am not sure whether it would affect other signals, so I still hope that you can capture the waveforms of this signal. A brief summary, ①when the RCK is grounded to GND, the SEROUT can be followed the sequence of SERIN, ②when RCK is high or pulses, the SEROUT is always zero?

If it's possible, could you do the test only for the first IC? Please provide a picture of the normal SEROUT of the first IC.

We will try RCK always high, thanks 

Thanks! and at the meantime, I think you can contact the local quality team, from the X-ray, it is clear to see the anomalous. and it would be more efficient to solve your issue.

RCK is always high and the behavior is strange, SEROUT follows the SERIN but 24 SRCK shift. It is abnormal. 

Thanks Jacky, I don't think it's an application issue, because only the abnormal IC can't work. you can do ABA test to verify it.

if it is a quality issue, we can't help you solve this problem. you need to contact the CQE and do FA analysis. 

Thank you, Hailee. We are in process.