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Short Circuit Testing

Raymond Koosha
Prodigy 10 points
Other Parts Discussed in Thread: BQ20Z45

Hi,

To test the reaction of bq20z45 to a short circuit, Pack(+) and Pack(-) nodes are momentarily shorted together.

This causes the Gate of Discharge FET(DSG) to go "LOW", opening the FET. In few cases the Discharge FET was damaged.

Are there alternative ways for such tests? Do TI recommend a safer way for the test?

All comments are welcome!

Thank you,

RK

  • 0
    Prodigy 40 points

    I'd like to know exactly how a short circuit is handled in the bq20z45.  Does the AFE OC Dsg/Time come into play here?  Is there an inherent delay in the AFE SC Dsg Cfg?  What if the AFE OC Dsg current trip is higher than the AFE SC Dsg Cfg current trip?  I guess what I'm looking for is the real mechanism of how a short circuit is handled.

    Thanks,

    Kit

     

     

  • 0 in reply to Kit Davis
    TI__Genius 14015 points

    Raymond,

    Shorting Pack+ and Pack- is the easiest way to test the SC performance. Are you using the EVM? We test this performance on the EVM and haven't noticed any damage to the DSG FET during short circuit.

    Kit,

    This timing diagram should help explain:

     

    The AFE SC Dsg level is the fastest acting overcurrent safety feature. It is possible to set the AFE OC Dsg level higher than the SC level, but to do this wouldn't be useful since the slower acting OC Dsg threshold would always happen later than the SC Dsg level. It would be like not even using the OC Dsg feature at all.

    Hope this helps clear things up.

    Regards,

    Jason

  • 0 in reply to Kit Davis
    Expert 2395 points

    Kit Davis,

    Yes there is delay in AFE SC DSG & OC DSG cfg & this delay is configurable to value provided only.Refer to page 6-7 of SLUA511 for more information.  Also mentioned is after what is change in fet & register values after SC detection.

     

    Regards

    Deepak