TPS65219: TPS6521903RHBR Power Up Issue.

Dear Team,

Also, one observation what we noted today was that we are not getting the output on GPO2 as well as per the Power-Up sequencing in TRM, The GPO2 should be coming out of PMIC at the first stage. But we are not getting that and now in this case the PMIC is still in Initialize state and not in the Active state.

Requesting TI to provide us the support at the earliest please as we need to deliver these boards by end of this week.

Thank you.

Regards
Amarnath G

Hi,

Thanks for reaching out. Here are a few questions before defining the next actions for the debug:

• Who is supplying the 3.3V IO for the SoC?

• Where is the external pull-up resistor for the GPO2?

• What is "GSM_PWR_CTRL"? The TPS6521903 NVM has GPO1 disabled (low) by default and can only be released by I2C after the PMIC has finished the power-up sequence.

Thanks,

Brenda

Hi Brenda,

Thanks for the quick reply.

Hereby answering your questions.

• Who is supplying the 3.3V IO for the SoC?
• Ans: The 3.3V IO for SoC has been supplied from the buck regulator where the same 3.3V is also supplied to the VSYS pin of PMIC

• Where is the external pull-up resistor for the GPO2?
• Ans: There is a 10K pull-up for GPO2 which is used as Enable signal for the power switch.

• What is "GSM_PWR_CTRL"? The TPS6521903 NVM has GPO1 disabled (low) by default and can only be released by I2C after the PMIC has finished the power-up sequence.
• Ans: GSM_PWR_CTRL has just been used as IO for our GSM module which shall not be required at the moment.
  
  Hereby attaching the Power Switch, 3.3V Buck Converter & SoC power section for your reference.
  

Hi Brenda,

It would be great if you can share me your email ID to send you the schematic for better readable in PDF format.

My Email ID is amarnath.ganapathy@tessolve.com you can reach me there for better and clear readable schematic format.

Thank you.

Hi Brenda,

I also gave the VCC_3V3_SYS for SoC 3.3V IO by isolating the Resistor R124 from VCC_3V3_MAIN and wired it to VCC_3V3_SYS from C314.

But the issue still persists, and I am not able to get the output from GPO2 pin of PMIC.

Thank you.
Regards

Amarnath G

Thanks for sharing the schematic.

• Could you do a visual inspection to confirm R100 is installed? The schematic says "DNP".

• What peripheral are you supplying with the PMIC LDO1?

• Could you also share a power-up scope capture showing the signals listed below. Please use a small time scale (~4ms):
  • VSYS (VCC_3V3_MAIN)
  • GPO2 (TPS22965_EN)
  • BUCK2 (VCC_1V8)
  • LDO3 (VDDA1V8)

Thanks,

Brenda

Hi Brenda, 

Thanks for the quick response.

Please find below the inline response for your questions.

• Could you do a visual inspection to confirm R100 is installed? The schematic says "DNP".
• ANS: Yes, R100 was DNP at the initial stage, later we mounted back the R100 with 0ohms and we observed that the VCC_3V3_SYS power switch was not enabling and hence no output found in VCC_3V3_SYS due to the GPO2 being low from PMIC.

• What peripheral are you supplying with the PMIC LDO1?
• ANS: PMIC LDO1 is VDDSHV_SDIO and is supplied only to VDDSHV5 pin (G17) of SoC with 0.1uF capacitor as decoupling.

• Could you also share a power-up scope capture showing the signals listed below. Please use a small-time scale (~4ms):
  • VSYS (VCC_3V3_MAIN)
  • GPO2 (TPS22965_EN)
  • BUCK2 (VCC_1V8)
  • LDO3 (VDDA1V8)
• ANS: Please find the attached scope shot below as requested above.
• 

Thank you.

Regards

Amarnath G

Hi Brenda,

Can we please get some breakthrough at the earliest.

As we need to deliver this project by end of this week, I sincerely request you to provide us your support by considering this as the high priority.

Thanks for the understanding.

Regards

Amarnath G

Hi Brenda,

Any update for the above thread please??

Regards 

Amarnath G 

We are reviewing the waveforms and schematic to identify potential issues.

• Why is the VSYS (VCC_3V3_MAIN) ramp unstable during power-up? Does it reaches 3.3V? The scope capture says 3.234v. 
• What components were uninstalled when the PMIC was isolated from ALL loads?
• There seems to be a backfeeding issue on Buck2. Even though the PMIC is OFF, the voltage at the output of Buck2 keeps rising. 

Thanks,

Brenda

Hi Brenda, 

Thanks for the response and below is the inline response for your questions.

• Why is the VSYS (VCC_3V3_MAIN) ramp unstable during power-up? Does it reach 3.3V? The scope capture says 3.234v. 
• ANS: Yes, the VSYS (VCC_3V3_MAIN) reaches 3.3V & the measured voltage is 3.321V
   
• What components were uninstalled when the PMIC was isolated from ALL loads?
• ANS: The following components were uninstalled to isolate the loads from PMIC.
  • R117 to isolate VCC_CORE
  • R185 to isolate VCC_1V8
  • L20 to isolate VCC_1V8
  • FL5 to isolate VCC_1V8
  • R132 to isolate VDD_DDR4
  • FL3 to isolate VDDSHV_SDIO
  • R15 to isolate VCC_0V85
  • R168 to isolate VDDA1V8
  • FL13 to isolate VDD_2V5
  • With the above components uninstalled we are able to achieve all the outputs from PMIC. And then only when R185 was reinstalled again we caught up with the same issue and the PMIC is not providing any outputs along with GPO2.
• There seems to be a back feeding issue on Buck2. Even though the PMIC is OFF, the voltage at the output of Buck2 keeps rising. 
• ANS: Yes, and we suspect this back feeding is from Processor only because as soon as we reinstalled the R185 the existing problem reoccurs (i,e.:              GPO2 is 0V & the output of BUCK-2 is 0.95V. 

Note: Hereby attaching the entire schematic section inclusive of PMIC, 3.3V Load switch & Full AM6321 section in the searchable format for better understanding.PMIC & AM6231.pdf

Hi Brenda,

It looks like there is some problem with BUCK-2 regulator and which is stopping the PMIC to come out of initialize state and enter into the active state.

Due to this BUCK-2 regulator issue we observe that GPO2 is also not been released from PMIC.

"We sincerely request you to provide your extended support on high priority basis please as we need to deliver this project by end of this week."

Thank you.

Regards

Amarnath G

Hi, 

Thank you for your patience as we support this request during working hours. I wanted to go back to one of the questions in my previous message, Why is the VSYS (VCC_3V3_MAIN) ramp unstable during power-up?

AMARNATH G said:

ANS: Yes, and we suspect this back feeding is from Processor only because as soon as we reinstalled the R185 the existing problem reoccurs (i,e.:              GPO2 is 0V & the output of BUCK-2 is 0.95V. 

Does this mean you don't see the issue when R185 and all the remaining load is disconnected from the PMIC?

Thanks,

Brenda

Hi Brenda,

Thanks for your reply.

Below is the inline response for your question.

Why is the VSYS (VCC_3V3_MAIN) ramp unstable during power-up?

And: We are looking into that part as well Brenda to make the VSYS ramp stable. One more input here we still isolated that VCC_3V3_MAIN from our board and we supplied through an external power supply which was stable but we still faced the same issue.

Does this mean you don't see the issue when R185 and all the remaining load is disconnected from the PMIC?

Ans : Yes we don't see the issue in PMIC when R185 and all the remaining loads are disconnected from PMIC.

Another observation is when we reinstalled the R185 again because that's the first output from PMIC we again faced the same issue of the back feeding of 0.95V on Buck-2 output and also the GPO2 not producing any output.

Thank you 

Regards 

Amarnath G 

Hi Brenda,

Any update please??

Thank you.

Regards 

Amarnath G 

Hi Brenda,

Any update please??

Thank you.

Regards 

Amarnath G 

Hi Amarnath,

If the PMIC works as expected when the load is disconnected and the sequencing matches the TRM timing diagrams on pages #8/9 then I don't see any issues related to the PMIC. It seems like you have a system level backfeeding issue that is affecting the PMIC because it is forcing a pre-bias voltage in one of the output rails. Have you get a schematic review from the AM62 processor team? 

Link to TPS6521903 TRM: https://www.ti.com/lit/pdf/slvucj2

Thanks,

Brenda

Hi Brenda,

Thanks for your response. In that case can you please help me to get the schematic review from AM62 processor team? If possible can you please loop Mr. Kallikuppa Srinivasa for schematic review. 

I would sincerely request you to make it as soon as possible please.

Thank you.

Regards 

Amarnath G 

Hi Amarnath,

I have transferred this E2E to the AM62 processor team. 

Thanks,

Brenda

Hi Amarnath, 

Can you help me understand if you reused the SK-AM62B-P1 schematics?

Regards,

Sreenivasa

Hi Srinivasa,

Thanks for your response.

Srinivasa, personally I am not aware of what schematic is been used as reference because I am involved in the 2nd iteration of this board. Whereas the AM6231 part is been reused from Iteration-1 itself. Also, the iteration-1 had no issue regarding the PMIC & AM6231 Booting.

Thank you.
Regards

Amarnath G

Hi Amarnath, 

I am not sure if the schematics is partial, With the available schematics   i have the below observations 

VCC_3V3_MAIN is a supply that is generated from the input supply and always available. Not sure why this is used to power the SOC IOs and the peripherals. 

vcc_3v3_sys does not seem to have been connected anywhere  Refer SK-AM62B-P1 schematics for the connections.

Many of the places where VCC_3V3_MAIN is connected should have been connected to vcc_3v3_sys.

Help me understand the reason for changing the 3V3_sys to 3V3_main.

Please compare with SK-AM62B-P1 and make the required changes. 

Regards,

Sreenivasa

Hello Amarnath

Thank you.

Can you please share the first iteration schematics. 

Regards,

Sreenivasa

Hi Srinivasa,

Good News!! now we are able to achieve the outputs in PMIC & also the processor, EMMC has been flashed successfully.

The problem was VDDSHV1 (Pin No: L18 & M19) was supplied with 1.8V, but we made use of an UART interface from VDDSHV1 bank where that UART transceiver was powered with VCC_3V3_MAIN. 

Hereby attaching the schematic screen shot of respective sections as given below:

1) VDDSHV1 POWER RAIL

2) UART INTERFACE SOC SIDE

3) UART TRANSCEIVER

Once we uninstalled the UART Transceiver IC (U30) we were able to successfully get the PMIC outputs as intended and also able to flash the EMMC successfully.

One question going forward for the next iteration can we supply 3.3V to VDDSHV1 pin no: L18 & M19?

Thank you.
Regards

Amarnath G

Hi Srinivasa, 

Below is the answer to your question.

We wanted to use the VCC_3V3_SYS for other peripheral and wanted the processor to control those peripherals during the low power mode and then we wanted the processor to go into the sleep state. For this reason, we thought the processor to be available even during the low power mode and have a full control of the peripherals.

Thank you.

Regards

Amarnath G

Hi Srinivasa,

Yes, I do agree with you that VCC_3V3_SYS has to connected to power the SoC IO's. and the same has been done in iteration-1 also.

I made this change in Iteration-2 for the reason which I mentioned in the above thread.

Can you please let us know since we are able to get the PMIC outputs as intended and also as we are able to flash the EMMC successfully though the VCC_3V3_MAIN has been connected to power the SoC IO's and peripherals. 

With these changes (i,e.: VCC_3V3_MAIN is used instead of VCC_3V3_SYS) are we good to go ahead and perform the functional test of the board?

Thank you.

Regards

Amarnath G

Hello Amarnath

Thank you.

Good to know you are able to resolve the issue.

Kallikuppa Sreenivasa said:

I am not sure if the schematics is partial, With the available schematics   i have the below observations 

Refer my comment on partial schematics. I do not see the UART included in the schematics provided.

For debug it helps if complete schematics is provided.

Regards,

Sreenivasa

Hi srinivasa,

Thanks for the quick response. In the above thread you can see the schematic screen shot attached for UART section. Can you please have a look into it and provide your comments.

Thank you.

Regards 

Amarnath G 

Hello Amarnath, 

You need to make sure the IO supplies to the SOC and the attached device are applied from the same source and ramp to-gather.

AMARNATH G said:

One question going forward for the next iteration can we supply 3.3V to VDDSHV1 pin no: L18 & M19?

Should be fine provided all the IOs connected to the IO group operate at same 3.3V level.

Regards,

Sreenivasa

Hi srinivasa,

You need to make sure the IO supplies to the SOC and the attached device are applied from the same source and ramp to-gather

Ans: As you can see in the previous attached schematic everything is been shifted to 3v3_main hence that should not be a problem right 

Regards 

Amarnath G 

Hello Amarnath, 

As i said, the schematics provided is partial and i cannot comment on the correctness.

If you can ensure there is no violations of fail-safe operation on the IOs between SOC and the attached device, that should be fine.

IO levels should match and input should be applied only after the supply ramps.

Regards,

Sreenivasa