LM25145: How to resolve the ringing

Hi Hale,

Yes, lots of ringing reflecting poor layout techniques. Send on the schematic, quickstart and layout for review. In the meantime, the customer can review app note SNVA803 for FET and input cap placement to minimize parasitics.

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Tim

Yes, suggestion is to follow the EVM layout template and refer to app note SNVA803 for power stage layout guidance.

In this case the return path from the input caps to the source of the low-side FET is quite long, increasing parasitic inductance and thus ringing. To mitigate this, consider using a resistor in series with the boot cap to reduce the high-side FET turn on speed. Also, an RC snubber from SW to GND is useful.

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Tim

Is there a quickstart calculator file I can review for this design? Maybe we can optimize the FET part numbers for lower noise.

It depends on the FETs, but a 2.2-4.7Ω boot resistor is a good starting point. And for the snubber try 2.2Ω and 220pF.

That FET has a very high Qrr of 111nC - try one with lower Qrr to improve the noise behavior, e.g. CSD18563Q5A.

See here for the quickstart: https://www.ti.com/tool/LM5145DESIGN-CALC

Yes, that is the connection, and the components are placed across the low-side FET. Qrr is basically charge that needs to be supplied to the low-side FET body diode when the high-side FET turns on. The resultant current is quite noisy. A lower Qrr FET will definitely help here.

\Check compensation with the quickstart calculator (make sure to enter derated value for Cout):

https://www.ti.com/tool/LM5145DESIGN-CALC

PS: note there should be a solid GND plane under the power stage components. And no SW vias or copper (as SW is a radiating plane with high dv/dt). Please follow the layout template in the LM5145 and LM5146 EVMs as well as the guidelines in the datasheet. There should be an AGND island for the small-signal components around the IC, this island connecting directly to the AGND pin and not tied to noisy PGND.

Regards,

Tim

This is likely a function of power-loop parasitic inductance and/or high-side gate loop parasitic inductance. Check the gate voltage of the low-side FET and ensure it is not reaching its Miller plateau voltage. Take a look at app note SNVA803 for power stage layout (FETs and input caps) and refer to the LM5145 and LM5146 EVM layouts as examples. Also, route the high-side gate drive traces short and direct to the FET as a differential pair.

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Tim