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UCC14141-Q1: Negative Rlim value

Nam, Dino
Expert 6445 points
Part Number: UCC14141-Q1
Other Parts Discussed in Thread: UCC14141EVM-068

Tool/software:

Dear team, 

The customer would like to use UCC14141-Q1 for bias supply. 

Customer specification is below. 

-  VDD : 2V, VEE : -18V 

But using calculator, As you can see below, we can see negative Rlim value. 

Q1, UCC14141-Q1 can't support customer specification? 

Q2, If it can support customer application,  Please let me know why Rlim value is negative. How can we fix Rlim2 value? 

Please refer to the attached and  let me know your opinion. 

UCC1414x-Q1_Calculator_V8_LS EMS.xlsx

Thank you. 

  • 0
    TI__Mastermind 33115 points

    When configured for dual output using a split capacitor output divider, RLIM works by sourcing/sinking additional current in/out of the capacitive divider midpoint. The voltage across the RLIM resistor is bound by VDD and VEE and along with the selection of RLIM, determines the max available source/sink current that can be used to help maintain change balance between the two output capacitor forming the capacitive divider. VDD=2V is to low to use RDR configuration but you can use a single RLIM resistor. Make sure your output caps are chosen as close as possible to the calculated values.

    Steve

      

  • 0 in reply to Steven Mappus1
    TI__Expert 6445 points

    Hello Steve, 

    Thank you for your comment. More questions 

    Steven Mappus1 said:
    VDD=2V is to low to use RDR configuration

    Is there Min voltage limitation of VDD  to use RDR configuration? 

    Steven Mappus1 said:
    you can use a single RLIM resistor.

    If we set 5mA for "Quiescent current of other load on (COM – VEE) except gate driver, IQ_OTHER_VEE" at above calculator sheet, As you can see like below, Single RLIM Resistor value is also negative. Is there Max quiescent current limit? 

    Can I promote this device for customer application , VDD : 2V, VEE : -18V ? please let me know your opinion. 

    Thank you.  

  • +1 in reply to Nam, Dino
    TI__Mastermind 33115 points

    When you see negative RLIM values in the calculation, this indicates the RLIM function will not be able to compensate for the total charge mismatch between the two series connected output capacitors. Ideally if C1*V1=C2*V2 the RLIM would be doing nothing to compensate. In reality the capacitor values will have some mismatch due to DC bias, temp, %tol, etc. When DC bias currents are mismatched between the two voltage rails, this adds an additional burden that sometimes cannot be compensated by RLIM. Then there is also the available voltage across RLIM needed to generate the compensating current...if the voltage is very low, it maty take more time to sink/source the current needed to achieve charge balance but if the time is to compensate (due to low current, dure to low voltage across RLIM resistor), it could be that the VDD or VEE voltage will trigger UVLO fault.

    Since the issue of charge balance is related to Q=C*V=I*t and then we add RLIM into the mix, there is no absolute answer to your question about what voltage is too low because it depends on cap value mismatch, bias current mismatch, available voltage across RLIM to generate enough RLIM current to overcome the voltage droop before UVLO fault is triggered. 

    99.9% of all use cases are the opposite of what you are proposing. For example, a more typical use for biasing a SiC/IGBT gate driver might be VDD-COM=+18V, VEE-COM=-2V. I would recommend to order the UCC14141EVM-068 and ask the customer to reconfigure the output, then load test the EVM under their test conditions?  

    What kind of application is requiring -18V/+2V?

    Steve

  • 0 in reply to Steven Mappus1
    TI__Expert 6445 points

    Hello Steve, 

    Thank you for your comment. 

    The customer application is SSR(Solid State Relay) and thew would like to use JFET like below. so they need bias voltage VDD-COM=+2V, VEE-COM=-18V. 

    If they don't use Rlimit (= 0 ohm), What kink of side-effect will occur?  please let me know your opinion. 

    Thank you. 

  • +1 in reply to Nam, Dino
    TI__Mastermind 33115 points

    For dual output, split capacitor configuration, you must include RLIM, either as single RLIM resistor or RDR configuration. 

    Steve