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TLV733P-Q1: SW frequency

Part Number: TLV733P-Q1
Other Parts Discussed in Thread: LMR43606-Q1, TLV733P

Tool/software:

Do you know what the SW frequency will be?
Is there a minimum ON time etc?
I think it will vary depending on the load capacity and load current, so I would like to see a graph or something.

  • Hello,

    You are thinking of switching converters.  The TLV733P-Q1 is a linear regulator.  Linear regulators do not have switching frequencies or minimum on time.  Please see this white paper for further details on the fundamentals of linear regulators.

    Thanks,

    Stephen

    slyy151a.pdf

  • Is there a formula to calculate the capacitance of the output capacitor to achieve the desired maximum overshoot?
    Also, is there a formula to determine the capacitance of the input capacitor?

  • Hello,

    There is no formula for this but you can review the datasheet for guidance for both the input and output capacitors.  See section 8.1.1 in the datasheet.  See also figure 8-1 for transient performance behavior depending on the load step for a 1uF output capacitor. In general, more capacitance on the output will limit the overshoot during a transient response.

    Thanks,

    Stephen

  • Is there a formula for calculating output ripple voltage?

  • You would use the PSRR curve data and assess the output voltage ripple based on the input voltage ripple.

    Example: lets say that the input voltage has 100mV of ripple at 1kHz.  When the LDO is loaded at 300mA, figure 6-9 suggests 50dB minimum of PSRR for this LDO.  Thus, the output ripple will become 100mV / (50dB) = 316 uV.

    Thanks,

    Stephen

  • I plan to use the LMR43606-Q1 in front of this LDO.
    I will use a switching frequency of 2.2MHz.
    Could you please provide me a graph with a PSRR up to 2.2MHz or above?

  • The PSRR data at frequencies above 1MHz is a function of the output capacitance and parasitic inductance.  In general, once the capacitor impedance curve resonates, the PSRR degrades.  What capacitors (values, case size, dielectric, and voltage ratings) do you plan on using on your output? 

    What PSRR do you need at 2.2MHz? We may need to suggest an alternate LDO if the TLV733P cannot provide the necessary PSRR at these frequencies.

    Thanks,

    Stephen

  • I plan to use a ceramic capacitor for the output capacitor with a capacity (recommended value ~10uF), size (1005 ~ 3216) and voltage rating of 10V.
    Does parasitic inductance refer to the pattern?
    Will there be oscillation if I connect it to the back of a 2.2MHz frequency step-down DCDC?

  • Using a 10uF 10V rated ceramic capacitor on the output of the TLV733P-Q1 should be fine. You are welcome to test with an EVM and your DCDC converter to confirm stability of each design using a load transient measurement and evaluating the ringing, or a NISM test.

    https://www.ti.com/lit/an/snoa507/snoa507.pdf

    https://www.picotest.com/solutions/non-invasive-stability-measurement/

    Thanks,

    Stephen

  • >The PSRR data at frequencies above 1MHz is a function of the output capacitance and parasitic inductance.

    Could you please tell me how to calculate it?

    Also, according to the Toshiba PSRR document below, it is written that it can be calculated if you know the output impedance(ZOFB) and the output resistance (rDS ) of the output PMOS(in the LDO), so could you please tell me these two?

    Simple Guide to Improving Ripple Rejection Ratio of LDO Regulators
    https://toshiba.semicon-storage.com/info/application_note_en_20210326_AKX00309.pdf?did=67686

  • The above impedance is for 2.2MHz.

  • The Toshiba document gives a very basic discussion.  Let me try to fill in some gaps:

    1. The output impedance is strongly a function of the load.  As load increases, the output impedance typically goes down.

    2. The ESL and parasitic PCB inductances play a significant role in PSRR at higher frequencies (100's of kHz to MHz).  The output capacitor resonates with the combined ESL and parasitic PCB inductance, and that is the frequency which you will see the peak PSRR.  The Toshiba document suggests PSRR is flat at high frequencies (figures 3.3.1, 3.3.4, 3.3.5, 3.3.6) but this inductance causes the PSRR to move back down (see any TI LDO datasheet PSRR curve, or the measurement on page 4 of the Toshiba document).  If you need a specific PSRR at high frequency then you must tune Cout (probably with several capacitors to account for tolerances) to cover the specific frequency range you are interested in.

    3. The peak PSRR is not just due to ESR but also the parasitic impedance on the PCB.  They sum together since they are in series.  Modern ceramic capacitors may have low values of milliohms of ESR so the PCB impedance may add 20-50% to this.

    4. In some LDO's there are additional PSRR enhancement feedforward loops, which are not included in the Toshiba document.

    We do not have the Rds of the pass device characterized.  To do so will require a strong business case for our engineers to open the transistor simulation and assess it, which will also take weeks to complete.  The output impedance of the LDO can be measured but it is a strong function of your operating conditions (load current, load capacitance, temperature, etc).  I would recommend obtaining an EVM and taking this measurement with your actual components and loading installed so you have the most accurate data possible.

    Thanks,

    Stephen