TPS3435-Q1: Safety behaviour

Willem Zwetsloot

Part Number: TPS3435-Q1
Other Parts Discussed in Thread: TPS36, TPS3436, TPS35, TPS3435

Tool/software:

Hi TI,

I'm working on a project using the TPS3435AFACADDFRQ1.

Now we use this watchdog timer as a failsafe circuit to make sure the system is safe when the system fails in software. We also also implement a 2 second delayed reset pin which asserts the watchdog timer manually.

We've been discussing the behaviour of our system in the case that the watchdog timer is faulty, our question to you is what is the behaviour of this chip when having an internal fault?

Is the output normally asserted and only non-asserted when the correct circumstances are present (timing pwm, state MR) or is it the other way around?

I hope to hear from you soon.

Kind Regards,

Max Overvoorde

3 months ago

0 Joshua Garcia 3 months ago

TI__Expert 6660 points

Hi Max,

I am looking into your inquiry and will provide a response by EOD 7/17 PST.

Thanks,
Joshua

0 Joshua Garcia 3 months ago

TI__Expert 6660 points

Hi Max,

The output of the chip is dependent on the random failure event that occurs within the chip. In Table 3-2 of the TPS3435, TPS3436, TPS35, and TPS36 Functional Safety FIT Rate, FMD and Pin FMA for Pinout A (https://www.ti.com/lit/fs/sffs599/sffs599.pdf?ts=1721235574272&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTPS3435-Q1)
we can see that certain failures cause the reset to falsely assert, others to remain asserts, and others early/late assertions. There is no clear answer as to a determined state if the watchdog timer has a random failure event.

Under normal operation with no random failure, the WDO remain unasserted when the correct circumstances are present.

Thanks,
Joshua

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TPS3435-Q1: Safety behaviour