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BQ40Z50-R2: SMBUS timeout

Part Number: BQ40Z50-R2
Other Parts Discussed in Thread: BQ40Z50

Tool/software:

Dear expert,

Randomly, BQ40Z50R2 SMBUS hang up at customer system. (SMBD keeps low and SMBC keeps high) 

It's very hard to reduplicate and capture SMBUS signal when problem happen.

They find BQ40Z50 has a timeout scheme which can be used as workaround. Their SoC pull SMBC to low for 50ms and then SMBUS can back to normal.

But I found Ttimeout should between 25ms to 35ms for 100KHz SMBUS speed. Is there any risk for their operation? Thanks

  • Hi Ryan,

    The SDA line being held low should only be possible if the device is in an ACK clock cycle OR if the device is transmitting data. If somehow the clock high timeout were to be disabled, then that could mean it is trying to transmit a '0' bit and isn't timing out. The typical way to address this is to pulse the SCL line until the SDA is released, then trigger a STOP condition to reset the bus. 

    Even though SCL high disabled should not be likely, there is no option for disabling the clock low timeout, so if pulsing SCL doesn't work you could also try holding SCL line low for 2 seconds. If the device SMBus engine is functioning this could trigger the 25ms SCL low timeout and reset the state. If somehow the SDA line is latched low even though the SMBus engine IDLE the 25ms might not trigger. Holding low for 2s I don't believe is a "reset" case on that device but it is worth a try to see if somehow the 2 second "bus low" timeout has any impact.

    The other things to look for off (more to check the state of the overall device, these won't explain why SDA is low):

    • Check for pulses on TS pin if possible, to confirm that the normal FW loop is running.
    • Toggle /PRES pin and see if FETs are responding. 
    • Discharge device to < 2800mV / cell (shutdown voltage) to cause shutdown and power back up, assuming above shows FW loop is running.
    • Check for damage to the device?