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TPS54620 phase delay between Enable pulled low to the Power Good Pulled Low

James Fuerherm
Prodigy 100 points
Other Parts Discussed in Thread: TPS54620

I have 5 TPS54620's and I am using the Power Good output for sequencing. I have the Enable line of the first sequential TPS54620 connected to a pull-down reset line. What is the time lag is between the Enable pin being pulled low and the Power Good pin being pulled low? If it is too long, I may have separate control for reset of each regulator but was trying to save on part count. 

  • 0
    TI__Guru**** 191445 points

    That is not specified or characterized.  From my lab data it is fast (instantaneous) if you are looking at it in the msec timeframe. Actually, the real question is "what is the delay from EN going low to the device entering shutdown?"  Depending on your load there may be additional delay for your output voltage to fall out of regulation and PWRGD going low.

  • 0 in reply to JohnTucker
    Prodigy 100 points

    Below is an excerpt from the datasheet on page 14. I interpreted this as saying the PWRGD signal could be independent controlled by the EN status. Did I interpret this incorrectly? Thanks.

     

    The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal

    reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN

    pin is pulled low or the SS/TR pin is below 1.4V.