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TPS25944L: UVLO event does caused a latched fault

Part Number: TPS25944L

Tool/software:

When an under-voltage limit is reached (4.4V in this case) the TPS25944L appears to limit the current output but does not assert FLTn or latch the output off.  Instead the output (VCC_5V_BST) starts ramping again which causes the input (VCC_5V) to droop again causing another UVLO event.  This creates a constant cycling that never recovers or latches into a fault state.  Why doesn't the fault state get latched?  What can be done to force this to a latched condition?  Below are the schematics for the eFuse and DC-DC connected to its output.

Circuit

  • Hi Rick,

    This is not an UVLO event. UVLO limit is 2.97V based on your schematic. This waveform also doesn't look like normal operation. Can you also probe current in same waveform. If current probe is not available, probe IMON pin. Please keep them in same waveform if possible.

    Best Regards,
    Arush

  • Hi Arush,

    Thanks for your response. I had changed R19 to 180K, so the UVLO is set to 4.4V.  I agree that this does not look normal but I have not been able to determine the root cause, which I'm hoping you can help me with.  Attached are an updated schematic that shows the changes that I have made.  I am also including 3 new waveforms that how IMON relative to VCC_OUT (VCC_5V_BST in the schematics) and VCC_IN (VCC_5V in the schematics).  The ILIM is set to 1.7A so I believe this is an under-voltage condition, not an over-current.  When I force an over-current I see a normal fault event (VCC_5V_BOOST goes low, FLT goes low).  But every under-voltage condition is always going into this cycling mode.  I did try changing dVdT to open and to 0.1uF.  It changes the waveforms but the cycling is present in both cases.

    What else could I check or tests could I run to determine the reason for the cycling instead of going directly to fault condition?

    Thanks,
    Rick