This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

BQ76952: AFE responds to OTP_WR_CHECK()(Subcommand 0x00A0) with 0xFF....

Part Number: BQ76952
Other Parts Discussed in Thread: MSPM0L1305,

Tool/software:

Hi,

I am currently writing firmware for a battery management system which features MSPM0L1305 and BQ76952 using Code Composer Studio.

I am currently implementing the OTP process and was able to successfully proceed up to step 8 described in the following documentation. However, when I send the OTP_WR_CHECK()(Subcommand 0x00A0) to AFE the reading from 0x40 to 0x5F are all 0xFF (i.e., 32 bytes of 0xFF's).

However, if I replace the OTP_WR_CHECK() subcommand with some random 2-byte number, for example 0x0000 or 0x1234, which are not defined as commands, surprisingly the reading from 0x40 is 0x80 which successfully moves the code on to the next step (i.e., step 10 in the documentation above).

Can anyone share some insights into this behavior?

Is there a certain case where the AFE fills the memory from 0x40 to 0x5F with the value 0xFF?

Thank you,

Kyungjae Lee

  • Hello Kyungjae,

    Returning 0xFF usually means a subcommand has not completed operation.

    Can you send a logic analyzer capture of each step?

    Best regards,

    Thomas Rainey

  • Hello Thomas,

    Thank you for your response.

    Please find the logic analyzer data (.sal) attached.captured during the execution of the following function which engages in the OTP steps.

    We have two BQ76952 chips on our board that are connected through the same I2C bus. The following function puts one of them into SHUTDOWN mode while changing the I2C address and OTPing it on the other:

    void BQ769x2_SetI2CAddrOTP(const uint8_t i2cTarAddr)
    {
        uint16_t batteryStatus = 0;

        if (I2C_TestTargetComm(i2cTarAddr) == OK)
        {
            // OTP has already been done, so return
            return;
        }

        // OTP has not yet been done, so perform OTP

        // Shutdown the redundant AFE
        DL_GPIO_setPins(GPIO_AFES_PORT, GPIO_AFES_RST_SHUT_R_PIN);
        TIMER_DelayMs(1500);
        DL_GPIO_clearPins(GPIO_AFES_PORT, GPIO_AFES_RST_SHUT_R_PIN);

        batteryStatus = BQ769x2_ReadBatteryStatus(AFE_DEFAULT_ADDR);

        // Ensure that the device is in FULLACCESS mode
        if (((batteryStatus >> BATTERY_STATUS_OFS_SEC0) & 0x03) == FULLACCESS)
        {
            // Enter CONFIG_UPDATE mode
            // - It is required to be in CONFIG_UPDATE mode to program the device RAM
            //   settings. See TRM for full description of CONFIG_UPDATE mode.
            CmdOnlySubcmd(AFE_DEFAULT_ADDR, SET_CFGUPDATE);
            DelayUS(8000);

            // Settings:Configuration:I2C Address
            BQ769x2_SetReg(AFE_DEFAULT_ADDR, I2C_ADDRESS, VAL_I2C_ADDR_NEW, 1);

            // Exit CONFIGUPDATE mode (Subcmd 0x0092)
            CmdOnlySubcmd(AFE_DEFAULT_ADDR, EXIT_CFGUPDATE);
            DelayUS(8000);
        }

        // I2C address change is applied on reset or when SWAP_COMM_MODE subcommand
        // is received.
        // NOTE: Due to the BMS 2.0 Rev1 hardware issue, reset couldn't be used.
        //       Consider changing this to resetting the AFE when the hardware
        //       issue gets resolved.
        CmdOnlySubcmd(AFE_DEFAULT_ADDR, SWAP_COMM_MODE);
        DelayUS(8000);

        // Ensure that the I2C address change has been successful
        ASSERT(I2C_TestTargetComm(i2cTarAddr) == OK);

        // Enter CONFIG_UPDATE mode
        // - It is required to be in CONFIG_UPDATE mode to program the device RAM
        //   settings. See TRM for full description of CONFIG_UPDATE mode.
        CmdOnlySubcmd(i2cTarAddr, SET_CFGUPDATE);
        DelayUS(8000);

        batteryStatus = BQ769x2_ReadBatteryStatus(i2cTarAddr);

        // Check if OTP conditions are met
        if (((batteryStatus >> BATTERY_STATUS_OFS_OTPB) & 0x01) == 0)
        {
            if (BQ769x2_ReadOTPWriteCheck(i2cTarAddr) == OTP_WR_CHECK_OK)
            {
                // All OTP conditions are met
                // Perform OTP and ensure that it has been successful
                ASSERT(BQ769x2_ReadOTPWriteResult(i2cTarAddr) == OTP_WR_RESULT_OK);
            }
        }

        // Exit CONFIGUPDATE mode (Subcmd 0x0092)
        CmdOnlySubcmd(i2cTarAddr, EXIT_CFGUPDATE);
        DelayUS(8000);

        // Wake up redundant AFE from SHUTDOWN mode
        DL_GPIO_setPins(GPIO_AFES_PORT, GPIO_AFES_WAKE_R_PIN);
        TIMER_DelayMs(WAKE_TIME_MS);
        DL_GPIO_clearPins(GPIO_AFES_PORT, GPIO_AFES_WAKE_R_PIN);
    } /* End of BQ769x2_SetI2CAddrOTP */

    Please let me know if you need additional information.

    Thank you,

    Kyungjae Lee

  • Hello Kyungjae,

    I am not seeing a logic analyzer capture. Can you reattach the logic analyzer captures for each step?

    Best regards,

    Thomas Rainey

  • It looks like the .sal file cannot be uploaded here. Do you have any alternative ways to receive the .sal file?

    Thank you,

    Kyungjae Lee

  • Hi Kyungjae,

    Can you try sending it through direct message?

    Best regards,

    Thomas Rainey

  • I tried to DM you but it didn't work as well. Can you see if you can access the file through the following link?

    https://drive.google.com/file/d/13FFQ8mRXJGjiGWLhzCe2AA55sWDM4Alv/view?usp=drive_link

    Thank you,

    Kyungjae Lee

  • Hi Kyungjae,

    I sent you a private message.

    Best regards,

    Thomas Rainey

  • Hi Kyungjae,

    After looking at the logic analyzer capture I think I found your issue. 

    Based on this section you have at least one safety fault triggered and OTP is blocked.

    Can you read all safety status registers to figure out which fault is triggered?

    Best regards,

    Thomas Rainey

  • Hi Thomas,

    My OTP process is used to separate the I2C address of the two AFEs and it is done before the AFEs are even fully configured for functionalities so I'm not sure if it makes sense to read Safety Status at the time of the OTP. The only things I ensured are, 10-12V is applied to the BAT and the TS pins are reading the room temperature.

    Is it a recommended process to configure the AFEs first, and then perform the OTP to ensure that there's no faults or failures represented by the Safety Status A/B/C while performing OTP?

    Can you let me know where I can find all the conditions I need to satisfy to successfully perform OTP other than the documentation I mentioned above?

    Thank you,

    Kyungjae Lee

  • Hi Kyungjae,

    Here is a helpful FAQSpecifically the last section, "I am using the SUV Permanent Fail in my system along with a fuse. How do I prevent my fuse from being blown after I program the OTP using the low 10-12 V supply?" should help with this issue. 

    Best regards,

    Thomas Rainey

  • Hi Thomas,

    Thanks for the information, it was very helpful.

    It appears to me that the key is to take the necessary measure to ensure that the BQ76952 is

    1. Applied 10-12V to the BAT

    2. of no faults

    3. of no permanent failures

    for the OTP process to be successfully done. And one of the possible ways to satisfy the condition 2 and 3 is to temporarily disable all fault and permanent failure detections before performing OTP.

    Could you verify if this is correct?

    Thank you,

    Kyungjae Lee

  • Hi Kyungjae,

    That sounds right! The only thing I would add is to double check the bit 7 of the 0x12 Battery Status():

    This will notify you if OTP is blocked or not.

    I may also add to use 12V to the BAT pin just to make sure there is enough voltage.

    Best regards,

    Thomas Rainey

  • Hi Thomas,

    Thank you for the clarification. I found in the TRM that the default setting for the "Settings:Protection:Enabled Protections A" is 0x88 which indicates that SCD and COV are enabled by default.

    Since, at the time of OTP, my board is not connected to the cell simulator, I assume that the cell voltage readings would have been all over the place, and it may have been COV that prevented the OTP.

    With that said, is there a good way to temporarily bypass the COV firmware wise? Or do I need to make sure that the board is connected to a cell simulator which will evenly distribute the supplied voltage (12V) to each cell so that COV is not triggered?

    Thank you,

    Kyungjae Lee

  • Hi Kyungjae,

    I recommend reading this thread it will have helpful information on this topic.

    Best regards,

    Thomas Rainey

  • Hi Thomas,

    My apologies for the late response. I think I have enough information to move forward. I will close the thread here and get back to you later if I come across other questions.

    Thank you,

    Kyungjae Lee