Tool/software:
Could you please provide the IBIS Model for Post-Layout simulation Signal integrity of Sync Signal (Externally Synchronized)
Thanks in advance
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Tool/software:
Could you please provide the IBIS Model for Post-Layout simulation Signal integrity of Sync Signal (Externally Synchronized)
Thanks in advance
Hey Belen,
We do not have an IBIS model for the device.
Note that the data sheet includes thresholds and rise times with a specific capacitive load to help estimate the behavior.
Thanks,
Daniel
Ok, I will emulate the behaviour.
Could you please confirm which would be the Cload to be considered when the Syn is used as Input?
Thanks
Hey Belen,
The Cload when Sync is used as an input will largely be dependent on your layout and the capacitive load of the board.
Pin to pin capacitance tends to be on the level of 10s of pF which can sometimes be dwarfed by the board capacitance.
If this value could be significant compared to board capacitance I can try and find an estimated value.
Thanks,
Daniel