BQ76952: About the use of LD pin of bq7695202

Hi Thomas,

bq7694202 design (default AFE first powered on, REG1 output 3.3V), I added the LD control circuit as shown in the attachment, applied to 7*3.2V battery, after AFE initialization, through REG2 to control the switch of Q1 and Q2, PACK+ and LD pins disconnected, so that when PACK+ has abnormal voltage, it will not abnormally wake up LDO REG1 through LD pin, resulting in B+ generating excess 300uA power consumption.

But as you can see, when the battery is shut down, it is found that REG1 (configured to 3.3V) is turned on to 3.3V voltage after being pulled down for tens of ms, resulting in an average power consumption of 14uA (the original schematic design LD is connected to PACK+ through R1+R2, and the power consumption after shutdown is <1uA), and it always exists, which is very strange. What state is AFE in? Can you analyze this situation?

Because you said that the LD pin voltage is floating, I tried to add a pull-down resistor to P- in R3, so that the voltage of the LD pin can be pulled to 0V during shutdown. I tested the R3 resistor, 10K and 100K. Because R1+R2 and R3 divide the PACK+ voltage, the voltage input to the LD pin is VLD=Vpack+ / (R1+R2+R3)*R3, but I found that the R3 resistance value does not affect the shutdown of the DSG. The voltage of DSG VGS is still around 10.6V when it is turned on and off. This is very strange. What is the function of the LD pin?

I checked the specification, and the DSG voltage will be pulled to LD and then discharged to VSS. This is inconsistent with what I tested, because R3 is 10K or 100K, which will cause the voltage input to the LD pin to be inconsistent. I don’t understand why the voltage input to the LD pin is different and does not affect the shutdown of the DSG. Can you please help evaluate whether my schematic and test results are reasonable? What I want to know is, if changing the input voltage of LD pin, will it affect the Vgs voltage of DSG and the shutdown of DSG? Or is there any risk? Please let me know, thank you.

Looking forward to your reply.

Hi Thomas,

1. As mentioned in the second paragraph of my previous reply, referring to the circuit added to the LD pin shown above, if LD is connected to the ground without an additional resistor, this will cause the AFE to pull down REG1 3.3V for 20ms and then reopen it when it is shut down (as shown in the waveform), resulting in an average power consumption of 14uA in the loop, which is unacceptable because the power consumption should be less than 1uA after a normal shutdown.
So what I want to know is, what state is the AFE in at this time? Which condition is not met, causing the AFE to be unable to enter the shutdown state? LD pin voltage or PACK+ voltage? Or something else?
I read your reply. When it is shut down, the LD pin has an internal 80KΩ pull-down, but this does not seem to work. Do you have any better suggestions?

2. As I said in the third sentence above, I tried to add a pull-down resistor to P- in R3, so that the LD pin voltage can be pulled to 0V when shutting down. I tested R3 resistance 100K. Because R1+R2 and R3 divide the PACK+ voltage, the voltage input to the LD pin is VLD=Vpack+ / (R1+R2+R3)*R3, but I found that the R3 resistance has no effect on the shutdown of the DSG, and the VGS voltage of the DSG is still around 10.6V when it is turned on and off. This is very strange, what is the role of the LD pin?
I also tried to add a 10K resistor between PACK+ and PACK-, but it didn't work.
The LD pin is pulled to ground by adding R3, and the AFE can enter shundown, but the LD pin voltage is not equal to the PACK+ voltage, so I want to know if this has an impact on the AFE turning on and off the DSG? Especially turning off the DSG when short-circuited. So I need your help to evaluate whether this design is feasible.

Looking forward to your reply, thank you.

Hello Zhang,

I will discuss with the systems engineer and get back to you by the end of the day (8/1).

Best regards,

Thomas Rainey

Hi Thomsa,

OK, please reply me as soon as possible. I need to design a schematic diagram and need your suggestions. Thank you.

Hi Thomas,

Thank you for your reply.
Then I design the schematic according to the circuit shown above. The LD pin is connected to PACK+ through R1+R2 and the R3 100K resistor is connected to ground. At the same time, the LD pin is disconnected from PACK+ directly through PMOS.

But I don't understand what you said about disabling REG2 before going into shutdown mode to make sure the FET is off.
1. Does RGE2 disable FET?
2. Enable REG1 and REG2 during AFE power-on initialization. My test found that REG1 and REG2 were turned off at the same time when the shutdown mode was entered. How do I disable REG2 before entering shutdown mode?
3, my BMS shutdown logic is to first send a command through MCU to shutdown the FET, at the same time, pull down the DFETOFF to ensure that the charge and discharge FET is closed, and then delay 10s or 1min to enter the shutdown mode, is this feasible?