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Original question:

TPS65219: Parallel LDO channels for higher current capacity

TPS65219: Can the maximum load capacitance of the channels be exceeded?

Valentin Stümpert
Prodigy 40 points
Part Number: TPS65219
Other Parts Discussed in Thread: TPS65215

Tool/software:

In our current design, we have selected the TPS65219 due to space constraints.

We use it power an FPGA, the recommended capacitance requirements of which are causing some issues for us in regards to the maximum capacitance figures that include point-of-load capacitance.

This is a problem with all three Bucks and LDOs 1 and 2.

As a specific example: Using Buck 1 to create a 0.85V core voltage rail, for which the FPGA forsees more than 500uF of capacitors.

Or using LDO1 for a 1.8V rail, that requires 60uF.

I understand that this usecase exceeds the recommended spec, but what problems would we be looking at for the operation here?

Is there any guidance as to how to proceed in this case?

Thank you, and kind regards,

Valentin Stümpert

  • 0
    TI__Mastermind 20066 points

    Hi Valentin,

    Thank You for using E2E. If the maximum output capacitance on the PMIC rails is exceeded, the phase margin starts to drop and stability gets affected.

    Just for reference, the TPS65219 PMIC has an option for "multi-PMIC operation" that allows to fully synchronize the sequencing between multiple TPS65219 devices. This feature might help to split the load/POL capacitance across the PMIC rails. Is this a non-automotive application? The TPS65215 has a 4x4mm package option that helps to keep the overall power solution small even when using 2x TPS65219 devices.  

    Let us know if you have any questions or need additional information. 

    Thanks,

    Brenda