TPS35: TPS35AA17AGADDFR TWD way too short

Marcel Robitaille

Part Number: TPS35
Other Parts Discussed in Thread: TPS3436, TPS3436-Q1, TPS36

Tool/software:

Hi,

I am experiencing a problem with the TPS35AA17AGADDFR chip. My CWD is 100nF and CRST is 1.5uF. I therefore expect TWD to be 0.495s (TWD=4.95e6 * CWD) and TD to be 7.42s (TD = 4.95e6 * CRST).

Here is my schematic. I know it's for a TPS3436. I had to switch for availability. The only difference in the pinout is the configuration pins, which I've labeled in blue.

Since RESET and WDO are anded in this variant, I expect pin 7 to stay low until SSTRT+TD. Then, I expect it to be high for TWD. This is not the case. When I give the chip power, pin 7 stays low for roughly 7 seconds. Then, it pulses high for only 8ms, and stays low for 7 more seconds.

Why doesn't it stay high for TWD after the reset? Why does it only stay high for 8ms?

I know TSD is 0 for my chip, but I still expect pin 7 to be high for TWD after startup and after TD.

I tried connecting a 1uF capacitor to CWD, but it had no effect. I also tried pulling SET1 high, which should multiply TWD by 128, but it also had no effect.

You can see this on my oscilloscope. Ch1 is pin 7 and Ch2 is VDD.

2 months ago

0 Jesse Villanueva 2 months ago

TI__Genius 14290 points

Hi Marcel,

Thank you for your inquiry, I will be happy to help. Could you please double check the state of the Pin 1? Since in your schematic it was used as SET0, but with the current device it is a MR pin, which will assert the WDO/RESET output if pulled low.

Jesse

0 Marcel Robitaille 2 months ago in reply to Jesse Villanueva

Prodigy 20 points

Hi Jesse,

Thank you very much for your response. I do not set any value on pin 1. I measured it at 3.3V, which must come from the internal pullup. I know my schematic is wrong. I'm treating it like a TPS35AA17AGADDFR.

0 Jesse Villanueva 2 months ago in reply to Marcel Robitaille

TI__Genius 14290 points

Hi Marcel,

What is WDO connected to? Are you able to disconnect the WDO from that input?

Jesse

0 Marcel Robitaille 2 months ago in reply to Jesse Villanueva

Prodigy 20 points

Hi Jesse,

It's connected to the enable pin of a TPS2557DRBR power switch. Sure, I can cut the trace. I should keep the pullup resistor though right?

Marcel

0 Marcel Robitaille 2 months ago in reply to Marcel Robitaille

Prodigy 20 points

Hi Jesse, There is no change after cutting that trace.

0 Jesse Villanueva 2 months ago in reply to Marcel Robitaille

TI__Genius 14290 points

Hi Marcel,

Were you able to test this schematic with the TPS3436 device?

Since the WDO is being continuously held low at start up, you have 1 of 4 causes.

VDD below Vit
MR held low
CRST or CWD unintentional grounding
excessive sinking current

Jesse

0 Marcel Robitaille 2 months ago in reply to Jesse Villanueva

Prodigy 20 points

Hi Jesse.

Thanks for the answer.

"Were you able to test this schematic with the TPS3436 device?" Unfortunately no. I had to switch to the TPS35AA17AGADDFR because I could not find the TPS3436 available anywhere. Do you know why that is BTW?

VDD below Vit: For this chip, Vit is 1.85V right? VDD is definitely above that.
MR held low: I measured it at high
CRST or CWD unintentional grounding: There should be capacitors, but maybe there is a fault in the soldering
excessive sinking current: This should not be the case driving the enable pin of TPS2557DRBR, right?

Thanks,

Marcel

0 Jesse Villanueva 2 months ago in reply to Marcel Robitaille

TI__Genius 14290 points

Hi Marcel,

For the first round of release of the TPS3436 we have only released the TPS3436-Q1 which is the AEC-Q100(automotive) certified version of the TPS3436. Same case for the TPS36 as well.(window watchdog + voltagesupervisor version of the TPS3436)

https://www.ti.com/product/TPS36-Q1

https://www.ti.com/product/TPS3436-q1

Yes, the TPS35AA17AGADDFR, threshold is 17*.05+1 = 1.85V.

Yes, having the RESET pin driving a high impedance input such as the enable pin of TPS2557DRBR should not be an issue.

Few more things that you can check:

impedance between RESET and ground, just want to make sure that the internal nmos is the one pulling the RESET low.
scopeshot of CRST and CWD during startup (since this device only takes the timing sample at startup then utilize an internal oscillator during operation.

Jesse

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TPS35: TPS35AA17AGADDFR TWD way too short