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TPS1211-Q1: TPS1211-Q1 for pre-charge

Scarlett Cao
Expert 4000 points
Part Number: TPS1211-Q1

Tool/software:

Hi team,

My customer wants to use TPS12111-Q1 to limit the inrush current and have questions about the precharge function.

They use 2 MOSFETs connected in parallel as the main FETs. In their application, the load capacitor is 2mF, the inrush current is about 100A and the max nominal current is about 89A. When the voltage of the capacitor is above a specific level, like 7V or 8V, the load will start to drawing current and then discharging the capacitor voltage. The precharge FET will need to tolerate a large current, which may damage the FET.

They now use TPS12110-Q1 on their board and reserve the design of TPS12111-Q1. They want to know whether it is feasible to add Rg and Cg to the gate of the main FETs (Q1 and Q2). According to the datasheet, it is not recommended, because the 2 FETs may have different parameters and will suffer different inrush current.

Do we have any experience in similar applications? Compared with adding Rg and Cg to the gate of the main FETs, Is there a better way to limit the inrush current in such scenario? Note that the end use case is zonal control module and customer do not have a clear idea starting from which voltage threshold the output will discharge, so they'll not be able to control INP and INP_G with output voltage monitoring, and there's no current sensing at pre-charge path. 

also would you pls share guidance how we get below equation 3)? the goal is to understand whether we could support enough current to overcome miller region with parallel FETs.

Thanks

Scarlett

  • 0
    TI__Mastermind 34935 points

    Scarlett,

    Thank you for the detailed post. I see what the concern is here- I am meeting with our backend team tomorrow to see if we have any design rooted mitigations here and will update you by EOD tomorrow (August 5th Dallas time). 

    For the equation- it is just plugging in known values specifically with the time constant (tau=0.63) into consideration. I will get more clarifications on the derivations as well. 

    Best Regards,
    Tim

  • 0 in reply to Timothy Logan
    TI__Mastermind 34935 points

    Scarlett,

    Conferring with the backend team, there are a couple of different ways to approach this.

    The first, and by far most common of which, would be to just use a FET on the precharge path with a higher SOA that could handle the additional inrush. The calculator here https://www.ti.com/tool/download/FET-INRUSH-SOA-CALC is a good tool to verify all of the parameters.

    You could also put a series resistor before Q3 that would help limit the current in the inrush phase. For adding additional Rg and Cg components to the main Q1 and Q2 FETs- as the datasheet states this is generally hard to do as the FETs will have different parameters and the Rg and Cg components of one FET would affect the other, but this can be done and is ultimately up to the customer to verify the external FET functionality.

    Best Regards,
    Tim