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TPS3813K33-EP: TPS3813K33

Ankush
Intellectual 490 points
Part Number: TPS3813K33-EP
Other Parts Discussed in Thread: TPS3813-Q1

Tool/software:

Hi Team ,

 We are using ( TPS3813K33QDBVRQ1/SOT23-6 ) watchdog for voltage Supervisory .

WDR and WDT pin are connected to VDD , so triggering pulse time on WDI pin is 20msec at interval of 2Sec .

but before my MCU initialize watchdog IC sending resetting pulse .

can you suggest me what to do before initializing 

or how to configure TPS3813K33 IC 

Best Regards 

Ankush Tiwari 

  • 0
    TI__Genius 9880 points

    Hi Ankush, 

    Thanks for your question. Could you please provide a schematic and oscilloscope picture so I can better assist you. I want to check if you are experiencing an expected or unexpected behavior first.

    Are you seeing this reset assertion while powering up? If not, what is the voltage value at VDD pin?

    For a quick background, during power on, the RESET pin is asserted when the supply voltage (VDD) becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps the RESET pin is low as long as VDD remains below the threshold voltage (VIT).

     Best,

    Sila Atalar

  • 0 in reply to Sila Atalar
    Intellectual 490 points

    Hi Sila ,

    Thank you for reply ,

    I am attaching my schematic a watchdog IC is connected to MCU using WDI pin .

    and RST and NTRST is pin connected to MCU reset .

    I am not providing oscilloscope picture because device not even start .

    WATCHDOG-PDF.pdf

    Best Regards ,

    Ankush Tiwari 

  • 0 in reply to Ankush
    TI__Genius 9880 points

    Hi Ankush,

    Thanks for sharing the schematic. The connection for TPS3813-Q1 seems correct but want to check what is the purpose of CJP1? I can tell the jumper is separating the Watchdog from the whole circuit but it seems like it is also separating the pull up resistor.

    While you testing TPS3813-Q1, it's important for RESET to pulled up. Can you please check that is not causing the issue? 

    If you want RESET output  to be high you need to make sure  VDD> Vit and when there is a proper WDI signal and there is a proper pull up resistor.

    Thanks,

    Sila Atalar 

  • 0 in reply to Sila Atalar
    Intellectual 490 points

    Hi Sila , 

    Sorry for late reply ,

    the CJP1 jumper is for when we are not using watchdog feature we can disconnect it .

    But jumper is shorted properly we are getting proper pull up resistor  .

    I think it about timing of WDI pulse ,after initializing GPIO I am sending pulse for WDI ,

    But still it resetting . 

    Best Regards ,

    Ankush Tiwari 

  • +1 in reply to Ankush
    TI__Genius 9880 points

    Hi Ankush, 

    Thank you for letting me know that you have a proper pull up connected to RESET pin. Then, we need to check the VDD level and WDI pulse. 

    For VDD: 

    Can you please get a scope shot when the reset of the supervisor is released? 

    For WDI:

    1) Since the watchdog timeout pin (WDT) is connected to VDD, the timeout is 2.5 s. And when the window watchdog ratio pin (WDR) is connected to VDD, in this configuration the ratio is 1:127.7, the lower boundary is 19.6 ms.

    2) The device must detect a rising edge at the WDI pin between tboundary,max and twindow,min to prevent asserting a reset

    Please check 7.3.2 2 Implemented Window-Watchdog Settings and 7.3.2.1 Timing Rules of Window-Watchdog for more detail information

    If you can let me know what kind of pulse you are providing WDI, I can check and try to provide similar input in my end to replicate your case.

    Hope this helps!

    Best Regards,

    Sila 

  • 0 in reply to Sila Atalar
    Intellectual 490 points

    Hi Sila ,

    Blue one is TP8 WDI pin .

    Red one is Reset pin .

    this is scope image at power up

    after getting started  every time resetting pulse occur  .

  • 0 in reply to Ankush
    TI__Genius 9880 points

    Hi Ankush, 

    Thanks for the scope pictures. Power up seems okay.

    Ankush said:
    after getting started  every time resetting pulse occur  .

    It seems like the reset is asserting due to late fault. The WDI positive edge seems like comes after the assertion. Can you please send another WDI signal that has 300ms or 400ms  smaller period than this signal so that WDI positive edge will be occur in the window frame?

    Best,

    Sila