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TPS54A24: Schematic Review

dVIR Ihie
Prodigy 20 points
Part Number: TPS54A24

Tool/software:

We are using part TPS54A24RTWR to generate core  voltage in my design to Eth Switch IC, I try to run Webench and the results strangers 

The core voltage should be very accurate ( Typical =0.8V , MIN=0.77V, MAX=0.83V).

additionally, my board is very dense so so I don't want to put unnecessary BOM.

the approach in my HW team is to add capacitance as much as possible but for now, I can't do it if it not necessary.

Vin= 15V(ignore the 6V)

Vout=0.8V

Iout=6A

if It's overdesign let me know, in addition I don't want to be close to margin so please consider it.

  • 0
    TI__Expert 5458 points

    Hi Dvir,

    I have reviewed your schematic and have the following comments:

    - FSW: Based on the Ton min (max) of the device along with the Rrt(fsw), Vout and Vin based on your schematic, it looks like device may hit min on time and therefore skip pulses at light load. Ideally with the conditions you have, fsw(max)=330kHz. Currently you have fsw=972kHz which is too high.

    - Inductor: The inductor is to high for this design, you need something under 0.78uH. However if you reduce FSW=330kHz then you can keep L=1uH. Having wrong inductor can cause increase jitter and bad transient. 

    - PGOOD: I didn't see a pull up resistor in the schematic. If PGOOD pin is in use, we recommend a pullup resistor between 10 kΩ -100 kΩ to a voltage source that is 6.5 V or less as this is an open drain output pin.

    - COUT: seems to be ok

    - COMP: If FSW gets decreased to 330kHz, based on calculation, it is best to decrease Rcomp to 5 kΩ instead of 10 kΩ to have an stable bode.

    Regards, 

    Eileen