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TPS25981: Power-on vs output enablement: does EFUSE permit V_EN/UVLO assertion with V_IN = 0V

Jexy Liew
Prodigy 590 points
Part Number: TPS25981

Tool/software:

Dear Experts, 

Custer has questions regarding our TPS25981 power-on condition.

Q1

Does the TPS25981 support (V_EN/UVLO input = ASSERTED) when (V_IN power supply = 0V)?

 

Q2

For our application we need to know

  • Can we assert TPS25981 V_EN/UVLO any time during V_IN ramp up?
  • Or is the requirement to assert V_EN/UVLO after V_IN ramp completes?

 

BACKSTORY:

Customer will enable a TPS25981 at a power-on sequence start to perform fuse only function (not used as a power ON/OFF switch).

Need to know TPS25981 power-on sequence constraints to enable it.

Thanks,

Jexy Liew

  • 0
    TI__Mastermind 38135 points

    Hi Jexy,

    Can you describe this little more please?

    Jexy Liew said:
    to perform fuse only function (not used as a power ON/OFF switch).

    Regarding your questions.

    Q1. Device takes power from IN pin so if VIN < UVP, the EN high won't switch on the FET.

    Q2. Device can have both type of startup, i.e. startup with enable (enable given after Vin ramps up) and hot-plugging (Vin and enable ramps up together). When Vin becomes greater than UVP (2.53V), EN can be asserted high, and device will perform startup. 

    Best Regards,
    Arush

  • 0 in reply to Arush Gupta
    TI__Prodigy 590 points

    Arush,

    Thanks for your response. Please see more details below: 

    //=============USE CASE=============== 

    Platform has AUX power when VAC applied.

    AUX powers Platform management hw including FPGA.

     

    EFUSE connections:

    EFUSE Vin: Platform MAIN POWER domain connects MAIN POWER output directly to EFUSE Vin. FPGA enables PSU MAIN POWER after Platform management subsystem has booted.

    EFUSE EN/UVLO: connects to FPGA. FPGA available to assert EFUSE EN anytime after VAC applied. This is because FPGA is fully powered after VAC applied = Platform AUX power enabled.

     

    For Platform to run Compute workload: Platform enables PSU MAIN POWER output, and at same time enable EFUSES protecting PSU MAIN POWER output.

    EFUSES are protecting MAIN POWER PSU output.

    EFUSES will be enabled and remain enabled always until EFUSE auto-disables when reacts to FAULT event.

    //=============QUESTIONS===============

    Q: any special power sequence requirements needed to enable EFUSE EN/UVLO while EFUSE Vin is ramping from 0V?

     

    Q: can EFUSE support SIMULTANEOUSLY turn on MAIN power and enable EFUSES at same moment?

    In this scenario EFUSE VIN = ~0V when EN/UVLO = asserted, and VIN = PSU MAIN POWER will ramp up with EN/UVLO already asserted.

    Datasheet seems to indicate this is acceptable EFUSE power-on control.

    If EFUSE does not support this power on sequence, then FPGA will need to define an EFUSE power-on state mc to manage it.

  • 0 in reply to Jexy Liew
    TI__Mastermind 38135 points

    Hi Jexy,

    Thank you for explanation.

    Jexy Liew said:
    Q: any special power sequence requirements needed to enable EFUSE EN/UVLO while EFUSE Vin is ramping from 0V?

    No, the eFuse enable can be provided at any time. The device will handle the start.

    Jexy Liew said:
    Q: can EFUSE support SIMULTANEOUSLY turn on MAIN power and enable EFUSES at same moment?

    This is acceptable.

    In both cases, Vin abs max should not be violated so add TVS diode at input side and decoupling cap near the device. 

    Best Regards.
    Arush

  • 0 in reply to Arush Gupta
    TI__Prodigy 590 points

    Arush,

    Thanks for your support! Want to confirm then:

    PS25891 permits

    • OE assertion with Vsupply = 0V.
    • OE assertion is permitted while IC Vsupply pin voltage ramps up (0 <= Vin <= Vnormal).
  • 0 in reply to Jexy Liew
    TI__Mastermind 38135 points

    Hi Jexy,

    Yes, TPS25981 permits assertion at EN for both these cases. Just note that device won't perform startup if Vsupply < Vuvp.

    Best Regards,
    Arush