Tool/software:
Hello,
Using common source configuration, we occasionally have power-up failure.
We assumed it's related to the charge-pump cap versus input capacitance of the Mosfets :
the following results were obtained using 100nF charge pump cap, Q1 Ciss (8900pF Typ. and 11570pF max), Q2 (4670pF Typ. and 6230pF Max.) and CdVdT = 2x4.7nF
- Normal Power-Up :
CH1 : Output Voltage, CH2 Q1 Gate-Source Voltage, CH3 Q2 Gate-Source Voltage and CH4 : Enable.
- Power-Up Failure :
- When reducing the CdVdT cap to 4.7nF : We can still see some struggle to power up at the beginning.
- When Using 470nF Charge pump Cap ( which is higher than 10x(Ciss_Total+CdVdT). with 2x4.7nF CdVdT Caps :
470nF Charge Pump cap solved the issue, with an understandable additional delay (Delta_t of approx. 3ms)
Is there anything we missed here ? is there any risk of using 390nF/470nF ?
Thanks and Regards,
Yassine
