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TPS274C65: Inrush current control when channels in parallel configuration

Joe Thurston
Prodigy 10 points
Part Number: TPS274C65

Tool/software:

Hello,

My application requires driving a load necessitating a current limit beyond what is capable for one channel, so I am interested in the parallel channel capability.

My question is, when channels (1&2 or 3&4) are configured in parallel, is the parallel Icl setting in the DEV_CONFIG1/2 registers in respect to each individual channel (resulting in parallel Icl = 2 * DEV_CONFIG1/2 setting) or is it in respect to both channels combined (resulting in parallel Icl = DEV_CONFIG1/2 setting)?

I am also interested in which behaviour applies to the in-rush current setting too.

Many thanks!


  • +1
    TI__Mastermind 29480 points

    Hi Joe,

    Welcome to e2e!

    If you set both channels to, for example, 1A, then the current limit of the paralleled channels will be about 2A. This scenario is spec'd at the top of page 12 in the data sheet, and applies to the inrush period as well.

    If using parallel channels, please be sure to set the corresponding PARALLEL bit(s) in the DEVCONFIG3 register.

    Thanks,

    Patrick