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TPS65987D: BC1.2 detection and IC boot up queries

Part Number: TPS65987D
Other Parts Discussed in Thread: TPS65987

Tool/software:

Hi Team,

My customer has BC1.2 detection and IC boot up queries as below. Could you please help to advise?

Thanks!

BC1.2 detection related:
1. What's the trigger condition of BC1.2 detection? Can it be trigger by SOC manually?
2. Does DP/DN pin on SOC needs to be Hi-Z mode when BC1.2 detection is occurred?
3. If SOC Hi-Z mode is needed but SOC not supported, can one of the TPS65987D GPIO be configed as USB switch control output to switch DP/DN out from SOC for BC1.2 detection? Will the below GPIO event ‘BC1.2_Host_Pull_Down_Enable_Event’achieve this function?



4. Does the DP/DN pull up and down during detection is controlled by TPS65987D, and no extra components is needed?

IC Boot up related:
1. For the external SPI FW flash, can we flash/update FW with test points that connected to others host(e.g. auto test station to flash FW on a new board)?
2. When plug-in adaptor with device in dead battery mode, inorder to only connect Vbus to PP_HV1(PP_HV2 keeps disconnected) can we use 'BP_ECWait_Internal ' boot config?

3.Can TPS65987D  detect both CC with Rp pull-up Debug accessory mode?
4.How long does it take for TPS65987D to cool boot up and dead-battery boot up (with external SPI flash) before it can detect DAM? We are considering using its GPIO to switch USB line to UART for boot up log capturing, it may needs TPS65987D boot up faster than SOC.


Best regards,

Terry

  • Hi Terry, 

    Please allow me some time to look into this and get back to you. 

    Thanks and Regards,
    Raymond Lin

  • Hi Raymond,

    Any updates here? Many thanks.

    Best regards,

    Terry

  • Hi Terry, 

    1. What's the trigger condition of BC1.2 detection? Can it be trigger by SOC manually?
    2. Does DP/DN pin on SOC needs to be Hi-Z mode when BC1.2 detection is occurred?

    Please refer to this application note on implementing BC1.2 support for TPS65987/8 series: slvae17a.pdf

    3. If SOC Hi-Z mode is needed but SOC not supported, can one of the TPS65987D GPIO be configed as USB switch control output to switch DP/DN out from SOC for BC1.2 detection? Will the below GPIO event ‘BC1.2_Host_Pull_Down_Enable_Event’achieve this function?

    If this GPIO event fit the criteria needed to indicate to the host pull-down/HI-Z state then it can be tied to one of TPS65987 GPIO pins. This is configurable through the Application Customization Tool which can generate the binary image needed to flash onto the PD controller. 

    4. Does the DP/DN pull up and down during detection is controlled by TPS65987D, and no extra components is needed?

    The DP/DN pins needs to be routed to specific GPIO on TPS65987D with no external components needed, refer to the previously attached Apps note as well as the datasheet for more details. 

    1. For the external SPI FW flash, can we flash/update FW with test points that connected to others host(e.g. auto test station to flash FW on a new board)?

    I'm not too sure what the ask here is, the SPI flash needed for TPS65987D should only contain the binary image generated from TPS65987D application customization tool. This SPI flash can be updated via SPI programmer such as the Aardvark adapter. When TPS65987D boots up either from VBUS or VIN_3V3, the PD attempts to read from the SPI flash connected to its SPI pin to load a valid configuration. 

    2. When plug-in adaptor with device in dead battery mode, inorder to only connect Vbus to PP_HV1(PP_HV2 keeps disconnected) can we use 'BP_ECWait_Internal ' boot config?

    This mode will allow VBUS to pass-through to PP_HV1 when booting up from dead battery mode (VBUS powers on first over VIN_3V3). 

    3.Can TPS65987D  detect both CC with Rp pull-up Debug accessory mode?

    TPS65987D supports debug accessory mode and can detect this through the CC lines. This is configured through Port Config (register 0x28), bit field 7. 

    4.How long does it take for TPS65987D to cool boot up and dead-battery boot up (with external SPI flash) before it can detect DAM? We are considering using its GPIO to switch USB line to UART for boot up log capturing, it may needs TPS65987D boot up faster than SOC.

    I do not have the exact timing information for boot-up from dead battery mode to detecting debug accessory. What is the timing requirement needed by the SoC for the PD to boot up before SoC is ready? 

    Thanks and Regards,

    Raymond  Lin 

  • Hi Raymond,

    Below is customer's feedback highlighted by blue. Could you please help to advise?

    Let me know if you prefer further discussion via Email. Thanks.

    2. Does DP/DN pin on SOC needs to be Hi-Z mode when BC1.2 detection  is  occurred?
    Please refer to this application note on implementing BC1.2 support for TPS65987/8 series: slvae17a.pdf
    Whether SOC DP/DN pin needs to be in Hi-Z mode when BC1.2 detection is occurred is not mentioned in the application note, can we assume it doesn't need a USB switch(SW2 in below PIC) when DP/DN of SOC not support Hi-Z mode?

    3. If SOC Hi-Z mode is needed but SOC not supported, can one of the TPS65987D GPIO be configed as USB switch control output to switch DP/DN out from SOC for BC1.2 detection? Will the below GPIO event ‘BC1.2_Host_Pull_Down_Enable_Event’achieve this function?
    If this GPIO event fit the criteria needed to indicate to the host pull-down/HI-Z state then it can be tied to one of TPS65987 GPIO pins. This is configurable through the Application Customization Tool which can generate the binary image needed to flash onto the PD controller.
    According to the Behavior note, this event seem to be used for BC1.2 Advertise mode, can we assume we need other signal to control USB SW(SW2) to switch USB signal from SOC to TPS65987D for BC1.2 detection if needed?

    1. For the external SPI FW flash, can we flash/update FW with test points that connected to others host(e.g. auto test station to flash FW on a new board)?
    I'm not too sure what the ask here is, the SPI flash needed for TPS65987D should only contain the binary image generated from TPS65987D application customization tool. This SPI flash can be updated via SPI programmer such as the Aardvark adapter. When TPS65987D boots up either from VBUS or VIN_3V3, the PD attempts to read from the SPI flash connected to its SPI pin to load a valid configuration.
    Sorry for we didn't make the question clear. We are planning to use below connection in our design that 1) To program the new builded board's empty SPI flash in production line with external SPI host in the test station. 2) To update the FW with OTA update through SOC SPI. Will this kind of connection cause any unexpected error for TPS65987D? Especially when TPS65987D boot up whit a empty SPI flash and then program the SPI flash with external host.

    4.How long does it take for TPS65987D to cool boot up and dead-battery boot up (with external SPI flash) before it can detect DAM? We are considering using its GPIO to switch USB line to UART for boot up log capturing, it may needs TPS65987D boot up faster than SOC.
    I do not have the exact timing information for boot-up from dead battery mode to detecting debug accessory. What is the timing requirement needed by the SoC for the PD to boot up before SoC is ready?
    The worst case we had in the previous project was device with battery attached and system on through debug cable plug-in, Vbus in to UART log print out time is around 270ms(See below waveform). Also does TPS65987D pass-through Vbus during it boot-up or after it boot-up? if it pass-through Vbus after FW loaded, the DAM detection should be no issue.

    best regards,

    Terry

  • Hi Terry, 

    Let me get back to you tomorrow on this. 

    Thanks and Regards,
    Raymond Lin

  • Hi Raymond,

    Looking forward to your reply.

    Thanks and regards,

    Terry

  • Hi Terry,

    I have given Raymond a reminder to look at this. He'll respond to your message soon.

    Thanks for your patience.

  • Hi Alex, Raymond,

    Any updates here? Many thanks.

    Best regards,

    Terry

  • Today is holiday in USA. Please allow some more time for Raymond to get back do you. 

  • Hi Terry, 

    Apologies for the delayed, please see my responses below:

    Whether SOC DP/DN pin needs to be in Hi-Z mode when BC1.2 detection is occurred is not mentioned in the application note, can we assume it doesn't need a USB switch(SW2 in below PIC) when DP/DN of SOC not support Hi-Z mode?

    What is the state of DP/DN of the SoC (floating, open-drain, push-pull)? Since BC1.2 relies on the DP/DM resistance measurement if the SoC introduces additional impedance/capacitance on the line during the BC1.2 enumeration it could cause faults. If the SoC does not support Hi-Z check to make sure in Port Control (reg 0x29) the Resistor15kPResent [24] is set to 0b:

    3. If SOC Hi-Z mode is needed but SOC not supported, can one of the TPS65987D GPIO be configed as USB switch control output to switch DP/DN out from SOC for BC1.2 detection? Will the below GPIO event ‘BC1.2_Host_Pull_Down_Enable_Event’achieve this function?
    If this GPIO event fit the criteria needed to indicate to the host pull-down/HI-Z state then it can be tied to one of TPS65987 GPIO pins. This is configurable through the Application Customization Tool which can generate the binary image needed to flash onto the PD controller.
    According to the Behavior note, this event seem to be used for BC1.2 Advertise mode, can we assume we need other signal to control USB SW(SW2) to switch USB signal from SOC to TPS65987D for BC1.2 detection if needed?

    Refer to the previous comment on the Port Control configuration. 

    1. For the external SPI FW flash, can we flash/update FW with test points that connected to others host(e.g. auto test station to flash FW on a new board)?
    I'm not too sure what the ask here is, the SPI flash needed for TPS65987D should only contain the binary image generated from TPS65987D application customization tool. This SPI flash can be updated via SPI programmer such as the Aardvark adapter. When TPS65987D boots up either from VBUS or VIN_3V3, the PD attempts to read from the SPI flash connected to its SPI pin to load a valid configuration.
    Sorry for we didn't make the question clear. We are planning to use below connection in our design that 1) To program the new builded board's empty SPI flash in production line with external SPI host in the test station. 2) To update the FW with OTA update through SOC SPI. Will this kind of connection cause any unexpected error for TPS65987D? Especially when TPS65987D boot up whit a empty SPI flash and then program the SPI flash with external host.

    This shouldn't be an issue, on the EVM the TIVA microcontroller is also connected to the on-board SPI flash that is also connected to TPS65987. After the SoC loads the PD config into the SPI lfash the PD needs to be power cycled for the new config to be loaded. 

    4.How long does it take for TPS65987D to cool boot up and dead-battery boot up (with external SPI flash) before it can detect DAM? We are considering using its GPIO to switch USB line to UART for boot up log capturing, it may needs TPS65987D boot up faster than SOC.
    I do not have the exact timing information for boot-up from dead battery mode to detecting debug accessory. What is the timing requirement needed by the SoC for the PD to boot up before SoC is ready?
    The worst case we had in the previous project was device with battery attached and system on through debug cable plug-in, Vbus in to UART log print out time is around 270ms(See below waveform). Also does TPS65987D pass-through Vbus during it boot-up or after it boot-up? if it pass-through Vbus after FW loaded, the DAM detection should be no issue.

    It should not take more than 270ms for TPS65987D to load a config from the SPI flash.  For the second part, as long as the DB config is set to BP_NoWait TPS65987D will not enable the PP_HVx untl a config is loaded from the SPI flash:

    Thanks and Regards,

    Raymond Lin

  • Thank you Raymond! I am clear now.

    Best regards,

    Terry