UCC28070: PFC application

Hello Renan, 

I wish to point out that 300ms is much more than "a few milliseconds"; it represents 15 full cycles of 50Hz.  
During this time, the output voltage can fall significantly out of regulation (depending on load level) and the VAO output voltage can saturate high to its clamp level. 

Under those conditions, the duty cycle is maximum and inductor currents can reach excessive levels when the AC line recovers (especially at high line). 
Normally each channel's peak limit (set by PKLMT pin) should limit how high the currents can get cycle-by-cycle, and the circuit should be designed to accommodate these peaks. 
I don't know if the TIDA design has been tested under the AC drop-out conditions which you describe. 

In any case, if there is significant time delay from the moment that the peak current crosses the intended limit threshold to the moment when the MOSFETs actually turn off, the turn-off delay may allow excessive peak current with may saturate the inductor and/or exceed the MOSFET rating.  
For example, if you expect to limit the drain current to10Apk (for example), but total turn off delay results in an additional 1us conduction time, the current may have risen to 20Apk before the MOSFET actually turns off and overstress of the FET occurs. (This is an example only.) 

Turn-off delay can come from limited bandwidth of the current-sense amplifiers, excess R-C filtering at CSA, CSB inputs, PKLMT comparator to gate-drive propagation delay (<100ns), and gate-voltage discharge time delay.    

Please check all of the time delays involved and determine how high Ipk may rise during the total delay and verify that the power components are suitably rated to withstand the worst-case peak current (usually at highest input voltage). Identify and rectify any blocks where the time delay can be reduced to avoid excessive over-design of the power stage. 

Regards,
Ulrich