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LM66100: LM66100 permanent damage.

Akshay Damare
Prodigy 40 points
Part Number: LM66100

Tool/software:

Hello,

We are using LM66100 ideal diode in our application. We have used this chipset for OR-ing of two supply voltages.

Below are the power rail information for which we have done OR-ing.

1. 4V output voltage comes from LDO output.

2. 2.7V-4.2V output voltage which comes from supercapacitor backup voltage (This power we have switched through the ideal diode while input power disabled.

Below is schematic diagram of logic we implemented.

Working of circuit:

When input power is present the ideal diode is turned off: VCE-VIN= 5.3V - 4.2V (Supercap voltage)> Turn ON threshold limit (80mV). In this case output circuitry will take power from LDO.

When input power is absent the ideal diode will be turned on: VCE-VIN= 0V-4.2V (Supercap voltage) > Turn OFF threshold  (-80mV). In this case our output circuit will take power from supercap through ideal diode.

This logic works fine in lab testing with number of turn ON/OFF cycles as well. But in some unknown scenario and cases the ideal diode gets permanently damaged. 

One of the known reason we found is we observed CE pin behavior on DSO and its too much sensitive to the noise in the presence of 1M ohm pull down as well. So that is know reason. To overcome this we have added 0.1uF capacitor on CE pin and we observed noise gets reduced by adding capacitor.

Still we are facing this issue of permanent damage of ideal diode, where we have observed that input and output of ideal diode is getting shorted. 

So kindly help us to resolve the issue, We are in mass manufacturing of the boards and 10% is the rejection due to this ideal diode chipset.

Thanks,

Akshay Damare.

  • 0
    TI__Mastermind 47955 points

    Hi Akshay,

    As stated, that the login works fine in lab testing. Do we know under what conditions is it failing? Is the CE pin violating its abs-max during ringing or noise?

    Regards,

    Shiven Dhir

  • 0 in reply to Shiven Dhir
    Prodigy 40 points

    Hi Shiven,

    We have checked CE pin voltage while testing its not crossing the abs-max. We have checked resistance of CE pin as well with respect to ground and its not changed.

    We have done below test conditions for reproducing failure condition:

    1. Switching VCC_4V on main power and supercapacitor power through ideal diode with ON/OFF interval from 15 sec- 5 min and load current of 1A.

    2. Switching load ON/OFF of 1A on the output of ideal diode with time time interval from 100m Sec- 1 Sec.

    3. We have kept both input power (VCC_5V3) and Supercap power which routed through ideal diode. In this mode only reverse current flow is there but no damage condition observed for ideal diode.

    We have not observed any failure condition with this test scenario.

    Can you please suggest what will be the failure condition in our case from our circuit diagram.

    Regards,

    Akshay Damare.

  • 0 in reply to Akshay Damare
    TI__Mastermind 47955 points

    Hi Akshay,

    Thanks for the information

    From your conditions and schematic, I don't see any abs-max violation.

    Are we able to reproduce the failure in any way? This can help in measuring all the pin voltages under fail case.

    Do you expect any kind of transients?

    Is the VCC_5V3 a stable supply?

    Regards,

    Shiven Dhir

  • 0 in reply to Shiven Dhir
    Prodigy 40 points

    Hello Shiven,

    No, we are not able to reproduce the failure with any defined process. We had kept the circuit switching between main 12V/24V supply and ideal diode supply for every 5 mins for 4 days. We did not observe any failure on that set-up. 

    We are not expecting any transients, not even transient current of output capacitor charging as capacitors would always be charged when system switches to ideal diode. 

    The VCC_5V3 supply is also stable. 

    Let us know if you need further details to investigate. 

    Thanks,

    Ajinkya Gorhe 

  • 0 in reply to Akshay Damare
    TI__Mastermind 47955 points

    Hi Ajinkya,

    It is clear that there is no inrush current since capacitors are charged.

    Since the rejection rate is 10percent because of fail, how are we finding that fail is happening?

    Do we test the ideal diode, and then move ahead in the mass production and when the IC is on the board, IN to OUT is shorted?

    Regards,

    Shiven Dhir