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TPS929120-Q1: TPS929120-Q1

Stefan Dominte
Prodigy 10 points
Part Number: TPS929120-Q1

Tool/software:

I am currently performing some functionality tests for the TPS929120-Q1 and I encountered some interesting behaviors.

As a test environment we use a power supply set to 12V and 3 output channels for the TPS929120 using R(Ref): 12.7kΩ, K(Ref): 64, CONF_IOUTx0-2: 29, CONF_PWMFREQ: 500Hz, CONF_ADCLOWSUPTH: 5V and CONF_WDTIMER: 0. We are using Linear Brightness Control with CONF_EXPEN: 0 and dithering disabled CONF_PWMLOWOUTx: Fh and cyclically read the FLAG0 register every 10ms for error detection.

The interesting behavior appears when we make an output request for two channels at the same time, but I managed to reproduce the behavior less often on a single output channel. The request is processed, the channels light up and remain lit without any flicker, but the internal register FLAG0 Register (Offset = 70h) makes a toggle with the following values: 0x03, 0xA0, 0xAC, 0xFD with the output of the channels not being interrupted.

We started to investigate the behavior internally and for tests we checked with an oscilloscope the lines VLDO:5V, SUPPLY:11.8V and nFLT: when the channel is activated, is pulled down for 50uS. We also manually read the voltage reported internally on ADC channels using CONF_ADCCH register and when output channel is ON the driver does not report a stable voltage for the Supply through the ADC channel, although on the oscilloscope the voltage remains stable at 11.8V.  

Our expectation was that when the FLAG 0 register toggles through the previously mentioned values, the driver should follow the behavior mentioned in chapter 7.3.5 Diagnostic and Protection in Normal State, and for example if FLAG0:3 and Supply UVLO is reported by driver the device to switch on POR state with all channels output OFF but the channels are still ON.

We are waiting for recommendations from your side with the tests that we can do continue to find out what leads to this behavior.

  • 0
    TI__Genius 10080 points

    Hi Stefan,

    Please provide a schematic of your test, and what do you mean "interesting behavior"? for FLAG0 register, do you mean the register value would be changed from 0x03 to oxFD?

    For example, if you want to test the UVLO function, you need to control the supply or VLdo voltage drops below its UVLO threshold. Thanks!

  • 0 in reply to Hailee Xu
    Prodigy 10 points

    Hi,

    I don't know exactly what is your expectation to receive regarding the "schematic of my test".

    The interesting behavior related to FLAG0 is that the register changes continuously it's value when channel output is on from 0x00 to 0x03 to 0xA0 to 0xAC to 0xFD without fulfilling "Fault action" described in chapter 7.3.5 Diagnostic and Protection in Normal State. The UVLO was only an example, although I tested the supply line with the oscilloscope and saw a voltage of 11.8V the UVLO fault seems to be reported by the driver by receiving the 0x03 value on FLAG0 register. From our perspective it seems that the driver transits the errors without "detection criteria" being fulfilled and without performing "fault actions".

    Thank you.

  • 0 in reply to Stefan Dominte
    TI__Genius 10080 points

    Hi Stefan,

    If you readback the status of FLAG0, you should follow below frame, I am not sure why do you get these values. please check this read process.

    The purpose of asking schematic is to check the HW connection of this device and to see how you do the test. Thanks!

  • 0 in reply to Hailee Xu
    Prodigy 10 points

    Hi,

    The Read frame is implemented as your picture from data sheet, valid data is read on FLAG0 register.

    Unfortunately we cannot share the HW schematic here on the forum, we are trying to find an alternative solution to do this.

    Thank you.

  • 0 in reply to Stefan Dominte
    TI__Genius 10080 points

    Hi Stefan,

    If you read from the FLAG0, it's supposed to be FALG0 data + CRC data. For example, if the FLAG0 shows 0x03, means the power-on-reset flag and error output flag is set to 1. You need to clear them first, if you first power the device, the device automatically switches to INIT state from POR state with FLAG_POR and FLAG_ERR set to 1. more details please see 7.4 Device Functional Modes of the datasheet. Thanks!

  • 0 in reply to Hailee Xu
    Prodigy 10 points

    At INIT state we clear the FLAG0 with the value 3, the toggle of the values described are happening at run time.

  • 0 in reply to Stefan Dominte
    TI__Genius 10080 points

    Hi Stefan,

    What is the FLAG0 status when it is in normal status? 0xA0 to 0xAC to 0xFD is supposed to be CRC data or something else. For example, if this device is not in Fail-safe mode, the FLAG_FS is 0, it won't be 1. and if you look at the Table 7-3. Diagnostics Table in Normal State in the datasheet, for some faults, there is no fault action, only registers and ERR pin would respond. Thanks!