TPS548B22: Jitter test

Hailiang Zhang 

The jitter seen in constant on-time control, like D-CAP and it's derivatives, and fixed frequency, is different, so the measurement technique and thresholds are different.

In fixed frequency trailing edge-modulation voltage mode control, which is a form of Pulse Width Modulation (PWM) jitter is measured by the variation in the On-times under steady state condition.  This is measured by triggering on the rising edge of the switching node and monitoring the falling edge of the switching node of the same pulse.  Using statistical analysis or more commonly using oscilloscope display persistence the range and distribution of the pulse widths are measured with variation equal to 10% of the nominal on-time generally considered stable and well behaved as long as the distribution does not develop a "bimodal" appearance, with two regions of jitter separated by an "eye" between them.

In constant on-time control, which is pulse frequency modulation of a fixed on-time, the on-time jitter measured above is typically very low, similar to the pulse frequency jitter measured fixed frequency applications.  Instead, we look for pulse frequency jitter or period jitter.  We still trigger on the rising edge of SW, but we look at the distribution of the next rising edges.  Again, we are looking for natural (also called gaussian) distribution of the period with a single central peak tailing off high and low as the pulse frequency modulates.  General guidance is that the pulse frequency jitter in steady-state (constant input, output, and load) should be less than 30% (+/- 15%) of the nominal switching period and with a single "mode".  If bimodal (alternating long/short switching periods) operation is observed, that is a sign that the loop bandwidth is too high (not enough output capacitance) and the loop is approaching sub-harmonic instability, much like current mode without slope compensation.

The last thing to check on the pulse frequency jitter is the jitter at the SECOND rising edge after triggered edge.  The jitter at the second edge should be equal to or less than the jitter measured at the first rising edge.  This is because COT should be a "self-correcting" control loop where any longer than nominal pulse should be followed by a shorter than nominal pulse.  As a result, the steady-state frequency jitter averaged over 2 cycles should be equal to or less than the jitter for a single pulse.