Other Parts Discussed in Thread: TPS6594-Q1
Tool/software:
Hi team,
Could you please provide power dissipation calculation sheet for TPS6593-Q1, also tr, tf and tdead for HS and LS FETs?
Regards,
Youhei MIYAOKA
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Tool/software:
Hi team,
Could you please provide power dissipation calculation sheet for TPS6593-Q1, also tr, tf and tdead for HS and LS FETs?
Regards,
Youhei MIYAOKA
Hi,
For the power dissipation calculation refer to the following efficiency calculator for TPS6594-Q1 device. Since the family and silicon is same only difference is functional safety features which do not affect the efficiency and power dissipation.
https://dev.ti.com/gallery/view/PMIC/PMIC-Efficiency-Estimator-Tool/ver/0.9.6/
For rise and fall times, you can use the Pspice model available on the product folder to calculate those things.
https://www.ti.com/product/TPS6593-Q1#all
Regards,
Ishtiaque
Hi Ishtiaque,
Thank you. I have some questions below:
1) Eff. Calculator tool is using , Rthjb, could you please check and provide calculation sheet with reference to Rthja
2) About rise time and fall times, these are the times for internal FET switch ON and OFF times, I am trying to calculate switching losses in the devices with the set switching frequency, I could not figure out these values from SPICE model, could you please help me with it
Regards,
Youhei
Hello Miyaoka-san,
1) Eff. Calculator tool is using , Rthjb, could you please check and provide calculation sheet with reference to Rthja
We do not have calculation sheets available for this specific device. We do offer the thermal resistances as per the datasheet though:
The link in the screenshot is located here: (click me)
2) About rise time and fall times, these are the times for internal FET switch ON and OFF times, I am trying to calculate switching losses in the devices with the set switching frequency, I could not figure out these values from SPICE model, could you please help me with it
We do have efficient data as well as the application curves in the datasheet. We do not specify times for the internal FETs as the control loop switches between PFM & PWM depending on programming, furthermore the datasheet says the PVIN & VCCA should not deviate from recommended, but also this shown in the absolute specifications below:
Please see section: 9.2.2 Application Curves for more information, if this still isn't enough, please do let me know.
Best Regards,
Nicholas McNamara