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TPS25990: Best way to do a complex power limit? (PCIe CEM specification requirement)

David Kraeutmann
Prodigy 50 points
Part Number: TPS25990
Other Parts Discussed in Thread: TPS25985,

Tool/software:

Hello,

PCIe 5.0 CEM specification has a complex power limit requirement, which can be seen here: https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/atx-version-3-0-multi-rail-desktop-platform-power-supply-design-guide/2.1a/pcie-add-in-card-power-excursions/

Implementing this requirement requires a TPS25990+TPS25985, as OC_LIMIT can be max. 27ms and the allowable excursion at 27ms is approx. 90A.

However this would set I_OCP at 90A, which means that a 63% overload condition can be present at all times, leading to an unacceptable 80K temperature rise at the connector.

What's the best way to ensure that the long-term current limit is followed?

For context, the application is a PCIe riser power delivery system where 600W add-in cards can be hot-inserted.