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UCC28950: Sharp drop in gain at switching frequency

Niall Smith
Prodigy 90 points
Part Number: UCC28950


Tool/software:

Hi,

I have recently been testing a phase-shifted full bridge design using the UCC28950 chip. It is a standard design implementation of the chip using PCMC.

In the open loop-response, there is a sharp drop in gain at the switching frequency (100 kHz) as seen below:

This appears to overlay the normal PCMC sub-harmonic peak at half the ripple frequency (100 kHz), as you can see the gain start to flatten out as it approaches 100 kHz.

This is also visible in the UCC28950 EVM open loop response bode plot, seen below:

I am wondering if this is standard behaviour? And if so, what causes it?

Thanks,

Niall

  • 0
    TI__Guru* 86286 points

    Hello,

    Your inquiry is under review and I will get back to you shortly.

    Regards,

  • 0 in reply to Mike O'
    TI__Guru* 86286 points

    Hello,

    Your behavior tracks the closed loop response in the EVM.  This appears to be normal.  Just double check to make sure that you have > 45 degrees of phase margin and greater than 3dB of gain margin and loop should be stable.

    To double check your stability you should also test the design under large signal transients; such as, load and line.

    Regards,