LM5156H: LM5156H: Boost converter 48V to 100V-250V

Hello Daniele Valente,

Switch node ringing is often caused by parasitics, so checking a transistor with a higher rDS(on), but lower gate capacitance might help.

When are you overheating these components? Do you have some metal for cooling connected to these?

Best regards,
Brigitte

Hello, 

thanks for the answer, I would try with a different mos. What do you think about "false trigger" please check the image attached?
I can arrange for a better power dissipation.

Thanks,
Daniele

Hi Daniele,

For reducing the ringing on the FET, you should place a snubber. Please have a look here:

https://www.omicron-lab.com/fileadmin/assets/Training_and_Events/Power_Analysis_and_Design-Symposium/2022/Presentation_BirichaDigital.pdf

To check what is going on at the switchnode it would be helpful to see a scopeshot that is showing VIN, Vout, SW and the gatepin signal in one scopeshot.

I am looking forward for your respose.

Best regards

Moritz

Hello Moritz, 

in attachment the requested scope signal with different X scale.
Yellow SW
Green Vin
Blue Vgate
Pink Vout

Please let me know if you need further info.

Hi Daniele,

How did you measure these waveforms? Is it possible that you had a long ground loop at your probe?

The switchnode behavior could also be DCM ringing. This would be normal and is caused by the FETs parasitic inductance resonating with the inductor. However, the shape looks somehow strange. Can you please add snubber networks across the MOSFET as well as across the diode and try again?

Best regards

Moritz

Hello Moritz, 

using a very short ground probe connection the waveforms are not changed.

I don't know how to measure the parasitic L as described in the omicron-lab doc.
The mosfet IXFA72N30X3 has an output capacitance of 300pF (energy related), the ringing is about 20MHz then L should be 34nH.
R=2*pi*50e6*34e-9=10.7~10ohms.
Using 100mW as power loss Csnub results (50e-3)/(350^2*240e3)=2pF, then a 2.2pF should work.

Is a 10ohms - 2.2pF snubber ok across mosfet drain-source?
What do you suggest to do with the diode ES3GH?

Thanks you, 
Daniele

Hi Daniele,

For the drain-source snubber, you can use 10 ohms and 2.2pF as a starting value. For the rectifier RC snubber please use this description for calculation:

https://www.ti.com/lit/ta/ssztbc7/ssztbc7.pdf

Or use the Powerstage designer, it has a tool implemented, that is using these formulas for calculating the snubber network. Also the powerstage designer is a very helpful tool for designing different power topologies : https://www.ti.com/tool/POWERSTAGE-DESIGNER#downloads

Can you please also share you layout files? (Best would be as PDF or altium files) Then i can check if maybe the layout can cause such resonances.

Best regards

Moritz

Hello,

I tried with both 10ohm-2.2pF and 12ohm-1nF across the MOS, in the second test (12ohm-1nF) I get lower ringing frequency and the peak is about 20V lower. But the circuit is still ringing a lot.
Layout file attached, U3 was not included in the schematic file, it's an high side switch BTS6163D used to turn the circuit on.

Thank you,
Daniele

CS1506_R2.pdf

Hi Daniele,

Is it possible to get all layers of the layout seperately? This would make it easier to analyze.

What i see is, that the switchode is very large. A large switchnode can cause a lot of parasitics and also can act as antenna which can lead to resonsnce effects. Thats why it is recommended to make the SW plane as small as possible.

You could try to operate in CCM. You would have to use a bigger inductor, a bigger slope compensation resistor and maybe a smaller sense resistor. The spikes at the switchnode will dissapear then an you will see if the gate signal still has this large ringing.

I recommend to use the quickstartcalculator in parallel with the powerstage designer for the calculations.

Best regards

Moritz

Hello,

then you suggest to use the device in CCM mode?
I'm worried about the parasitic resistance due to reflow soldering on the sense resistor.

Attached the layers file.

Many thanks,
DanieleCS1506_R2_layers.pdf

Now with correct file in attachment.
Sorry for the mistake.

DanieleCS1506_R2_separateLayers.pdf

Hi Daniele,

i recommend to try CCM to see the effects on the waveforms. It is possible, that the layout has to be improved for a proper DCM operation with these specs. Also CCM operation can reduce the heating of the inductor and FET.

For the next ckeck, please try also to put a 0Ohms gate resistor.

Best regards

Moritz