• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 63 subscribers
  • Views 519 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS3106E09---Input transition rise and fall rate at Δt/ΔV at MR

Peng Feng
Prodigy 10 points

Hello,

Now we use TPS3106E09 in our project.

I see that the maximum transition rise and fall rate of MR is restricted to 100ns/V from the datasheet (page3).

The following shows the MR input  test result of our project.

(Test 1) @U7  MR rise and fall rate measured value are 918081.21ns/V and 14031.66ns/V respectively.

(Test 2) @U8  MR rise and fall rate measured value are 877219.1 ns/V and 13683.27ns/V respectively.

From the data above, we can see that the test results are far more than the spec.

Please help to confirm the correctness of spec definition. Why does it define so quick transition rate?

Are the test results acceptable?

  • 0
    TI__Expert 8890 points

    Hello Peng,

    I apologize for my earlier answer.  This is easy to mis- interpret and so I will elaborate.  The data sheet specification for rise and fall times is standard for CMOS logic. It is well understood that CMOS circuitry does not perform well when nodes are left floating or when logic nodes are in that transitional region between states. It is standard industry practice to specify the maximum transition time between logic states to be 100ns/V - which is what the data sheet specifies.

    In your case, you are using much slower transitions (longer rise/fall times) between logic states. Although this may work for you, it is standard industry practice to use much faster rise/fall times. Texas Instruments cannot guarantee performance for logical transitions that are outside of specification.

    Regards

    Bill