Tool/software:
Hello,
I have modelled a few circuits with the LM61495 component to conduct efficiency tests but am running into a reoccurring issue where my efficiency calculations are exceeding expectations. The designs aim for 12Vout at 10A which is observed from simulation results. However, when implementing averaged input and output power traces to calculate efficiency, they seem to continuously converge and not reach a plateau even after letting the simulation run for longer than an hour, causing high efficiency results which I was not expecting. This is larger than what the LM61495 datasheet suggests with these circuit parameters, and after using the webench power designer tool to model a new circuit and creating this for simulation in Pspice for TI, similar results occurred leading to efficiencies 97%+, when webench calculated 96.9%. I have attached an image of the circuit used for this.
Additionally, whenever I try to adjust to 2.2MHz frequency at lower current configurations by grounding the RT pin, simulations show extremely large initial input current levels >25kA and I am unsure why. Is my method wrong for these?
Thank you.
