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Original question:

UCC28251: Enable functionality

UCC28251: Exiting Pulse Enable Mode

Justen Brown
Prodigy 20 points
Part Number: UCC28251

Tool/software:

The datasheet describes how to "enter" pulse-enable operation by sending a falling edge to EN pin prior to SS reaching 0.3V. Great.
As the other posts imply there are concerns with 'accidental' glitches causing the IC to enter this pulse-enable operation. I understand methods to mitigate the concern.

But in the event that it does occur - how do we 'exit' pulse-enable mode to go back to level-enable? Does it require a Vdd UVLO to reset IC to level-enable mode? Please elaborate on how to exit pulse-enable mode, ideally without power cycling Vdd.

  • 0
    TI__Guru 73825 points

    Hi,

    Fig 21 shows how level enable is made. Fig 22 shows how pulse enable is made. Comparing these two, you can see that they have the same start and same ending the difference is "level" keeps EN always high, "pulse" allows EN drops to 0 in the middle. So there is really no exit from "pulse" mode, if you keep EN "level" high for the whole time, then it becomes level enable. 

    If the above is not what you are asking, please draw a scheme of timing what you want to have so we can comment if ok or how to achieve.

  • 0 in reply to Hong Huang
    Prodigy 20 points

    Page 16 paragraph 1 referring to pulse enable mode states "....In this case, the next rising edge at EN pin disables the controller".

    Yet figure 22 shows that the SS/CLK are NOT disabling at the rising edge, but instead the falling edge:  

    So does the IC disable with with rising edge or the falling edge? If it's the falling edge, as the figure 22 shows. 

    The reason why I ask, is that I have gone into pulse-enable mode but exiting the mode was not seemingly possible without power cycling the IC. Hopefully I'm mistaken. Please advise. 

  • 0 in reply to Justen Brown
    TI__Guru 73825 points

    Hi,

    Falling edge disable for both "level" and "pulse" EN mode. 

    Note in "pulse", the first pulse falling edge has to be before SS < 0.3V (including noise everything), or the mode is "level".  

  • 0 in reply to Hong Huang
    TI__Guru 73825 points

    Hi,

    Falling edge disable for both "level" and "pulse" EN mode. Notice "falling" means the second pulse falling. Some people wants to use the first pulse falling edge to disable before SS reaches 0.3V, it is not possible. That is why emphasize the rising meaning the "pulse" EN needs to have a pulse after SS > 0.3V in order to disable the IC. 

    Note in "pulse", the first pulse falling edge has to be before SS < 0.3V (including noise everything), or the mode is "level".  

    Just to follow the two figures for timing of "level" and "pulse" EN and disable.