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UCC20225-Q1: Duty cycle lower than 50%

Ian Barrameda
Prodigy 10 points
Part Number: UCC20225-Q1
Other Parts Discussed in Thread: UCC20225, TPS2838

Tool/software:

Hi,

I want to use UCC20225 gate driver for the synchronous buck design. The design is 10:1 ratio. If the PWM duty cycle as input to the UCC20225, is 10%, would the other gate output become 90% (deadtime considered)? In other words, can I use this driver with below 50% duty?

If yes, how the will the controller knows if the pulse needs to be terminated already for the complimentary output if the controller does not have an information of switching frequency?

Thanks,

Ian

  • 0
    TI__Expert 7473 points

    Hi Ian,

    Our expert is currently out, and we'll get back to you by end of this week.

    Best,

    Pratik

  • 0 in reply to Pratik Adibatla
    Prodigy 10 points

    Thanks Pratik. As an additional question, I don't really need isolation for the driving. If I use UC20225, is it okay to have similar reference for both the input and output? In other words, can I use a single supply for the input (VCCI) and output (VDDA & VDDB)? Or is it possible to just use TPS2838 driver instead. Design is synchronous BUCK, 1kW.

  • 0 in reply to Ian Barrameda
    TI__Mastermind 23196 points

    Hi Ian,

    Yes, you can input any duty cycle that is needed. The minimum pulse width can be as low as 20ns into the gate driver, but it is likely that the driven FET will require a higher limit on the minimum duty cycle pulse width achievable.

    The outputs are complimentary, and the other side will turn off when the PWM input goes high. The controller that drives this gate driver will likely set a fixed switching frequency, and vary the duty cycle based on the loading conditions.

    You can use a non-isolated gate driver instead, which will be less expensive. TI has integrated synchronous buck converters if you need lower power and voltage. 

    Best regards,

    Sean