Tool/software:
I am carrying out spice analysis with the supplied TPS7H1101A-SP Transient Spice Model, specifically simulating SET on Vout rail in line with observations from the TI SET Test Report SLVK045.
The SET configuration in that report is for a single device, my configuration is for a parallel set of two devices. My main question for support is a correct methodology to simulate the SET droop, especially from a working assumption that a SET event will only affect one of the devices, not both at the same time; I would anticipate some compensatory interaction on the non-SET affected device.
I have looked at two possible approaches to simulate output rail deviation external to the models, but I would like some advice as to whether alternative steps or limitations exist?
Scenario one - Vout is momentarily switched into a fixed DC source set at % deviation of Vout - this is useful for understanding hold-up capacitor behavior, easily profiles to SET capture seen in the TI report but possibly not representative of SET interaction between the two devices.
Scenario two - FB voltage divider resistor values are momentarily switched to new values representing target % deviation of Vout - again possibly useful for understanding the recovery from SET, but possibly deficient for onset of SET.
