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TPS7H3301-SP: PGOOD Power On Behavior

John Lally
Intellectual 600 points
Part Number: TPS7H3301-SP

Tool/software:

Hello e2e,

    This question applies to a critical long duration space-flight mission.

If the PGOOD pin is pulled up to VDD/Vin=2.5V what is the behavior of the PGOOD pin during the interval when VDD/Vin is ramping up:

  1. PGOOD is low over entire interval while VDD/Vin is ramping ?
  2. PGOOD will follow VDD/Vin up to some voltage and then go low, i.e., some minimum voltage is required on VDD/Vin to guarantee PGOOD will be driven low?
    1. If this is the behavior, what VDD/Vin voltage level guarantees PGOOD will drive low?
  3. Some other behavior. If this is the case, please explain that behavior.

NOTE: VLDOIN will be Un-powered and the EN pin will be low during the interval when VDD/Vin is ramping up.

Thank you, -John

  • 0
    TI__Genius 11950 points

    Hi John,

    The second scenario should be correct. Since PGOOD is open drain, it should follow VDD/VIN until that rail reaches the UVLO threshold for the device to turn on internally. At that point, PGOOD would be in a defined LOW state. 

    Since it isn't explicitly described in the datasheet, let me sanity check the assumptions here and get back to you with confirmation.

    Thanks,

    Sarah

  • 0 in reply to Sarah Koch
    Intellectual 600 points

    Hi Sarah, any update on this question ?

    The answer may impact power sequencing circuitry and the release to fabrication of a critical space-flight PCB.

    Thanks Sarah, -John

  • 0 in reply to John Lally
    TI__Genius 11950 points

    Hi John,

    Apologies for the wait. I'm working on getting a board to confirm the functionality. Should have an answer for you in the next few days.

    Thanks,

    Sarah

  • 0 in reply to Sarah Koch
    TI__Genius 11950 points

    Hi John,

    Was able to run a test imitating your described conditions: PGOOD pulled up to VDD/VIN, EN=0V, and VLDOIN=0V.

    When VDD/VIN goes high PGOOD does indeed follow that rail until ~0.6V, at which point it becomes active and pulls the output into a defined LOW state. The threshold is approximately the same when VDD/VIN is falling during shutdown.

    Let me know if there is anything else I can clarify.

    VDD/VIN is blue. PGOOD is green.

    Thanks,

    Sarah

  • 0 in reply to Sarah Koch
    Intellectual 600 points

    Thank you Sarah that's helpful. 

    What would you recommend we use as a Minimum & Maximum for the VDD/VIN voltage level at which the PGOOD output drives low on way up and goes Hi-Z on the way down ?

    Chances are the 0.6V is typical, our circuitry needs to account for Minimum & Maximum levels.

    Thanks again Sarah.  -John

  • 0 in reply to John Lally
    TI__Genius 11950 points

    Hi John,

    Agreed that 0.6V is a typical value. Since this is not a parameter that has been tested across temp, process, operating corners, radiation, life, etc we're unfortunately not able to provide a min/max. 

    As a starting point at least, since we know this behavior is a result of internal circuitry transitioning from an undefined unpowered state to a defined powered state - the maximum VDD/VIN UVLO threshold (2.25V) could be considered as a very conservative max value. Even though voltages that high are likely overkill, the max for that parameter has been confirmed in testing.

    All the best,

    Sarah

  • +1 in reply to Sarah Koch
    Intellectual 600 points

    Thank you Sarah, we'll proceed accordingly. -John