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TPS6594-Q1: TPS65941515RWERQ1 SLVUCD4 Figure 3-2

Michael Vaughan
Prodigy 30 points
Part Number: TPS6594-Q1
Other Parts Discussed in Thread: TIDEP-01022

Tool/software:

The TIDEP-01022 schematic shows additional logic associated with the VDD1_LPDDR4_1V8 regulator enable that uses VDD_IO_1V8 in an OR arrangement together with GPIO6 as the enable. This appears to provide the required timing for the LPDDR4 VDD1 power ramp timing. Should SLVUCD4 Figure 3-2 be updated to reflect this additional logic to ensure LPDDR4 power ramp timing is met?

  • 0
    TI__Guru 52465 points

    The logic is required only if supporting a special low power mode.  Suspend-to-RAM is a low power mode with everything powers off except the SDRAM - which id kept in self refresh.  This logic is used to control the DDR's 1.8V power rail.  If that low power mode is NOT used, then this circuit can be removed and VDD_IO_1V8 can be combined with VDD_IO_1V8

  • 0 in reply to Robert Eschler
    Prodigy 30 points

    Thanks Robert. As I see it the SLVUCD4 application note should provide two connection arrangements:

    1.  VDD1_LPDDR4_1V8 should be connected directly to VDD_IO_1V8 (no low power mode)

    2. VDD1_LPDDR4_1V8 should be connected as in TIDEP-01022 which provides the OR arrangement for VDD_IO_1V8 and GPIO6

    Enabling the VDD1_LPDDR4_1V8 regulator using GPIO6 only as in SLVUCD4 Figure 3-2 will not work as shown.

  • 0 in reply to Michael Vaughan
    TI__Mastermind 20439 points

    Hello Michael,

    After looking at the schematic among other documents you are correct, of all other discrete power resources that are enabled by the PMIC that this logic is not present on the APP note for SLVUCD4. We will take this into account with an app note update in the follow relevant sections both in word & diagram.

    Michael Vaughan said:

    1.  VDD1_LPDDR4_1V8 should be connected directly to VDD_IO_1V8 (no low power mode)

    From Robert's response, my expectation is that VDD_IO_1V8 is to be kept the same and not connected to the OR circuit for this non existent circuit in the absence of a low power mode, not that VDD1_LPDDR4_1V8 should be connect to VDD_IO_1V8. Robert, can you clarify?

    BR,

    Nicholas

  • 0 in reply to Nicholas McNamara
    TI__Guru 52465 points

    If the LPDDR4 low power mode is NOT used, customer can either use VDD_IO_1V8 to enable the regulator (remove OR gate logic) or remove the regulator and combine VDD_IO_18 and VDD1_LPDDR4_1V8.